mirror of https://github.com/YosysHQ/yosys.git
extract_counter: Fix clock enable
This commit is contained in:
parent
12fa4a3121
commit
5fc180ed2d
|
@ -509,13 +509,15 @@ void counter_worker(
|
||||||
cell->setPort(ID(CE), extract.ce);
|
cell->setPort(ID(CE), extract.ce);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
|
{
|
||||||
cell->setParam(ID(HAS_CE), RTLIL::Const(0));
|
cell->setParam(ID(HAS_CE), RTLIL::Const(0));
|
||||||
|
cell->setPort(ID(CE), RTLIL::Const(1));
|
||||||
|
}
|
||||||
|
|
||||||
//Hook up hard-wired ports (for now up/down are not supported), default to no parallel output
|
//Hook up hard-wired ports (for now up/down are not supported), default to no parallel output
|
||||||
cell->setParam(ID(HAS_POUT), RTLIL::Const(0));
|
cell->setParam(ID(HAS_POUT), RTLIL::Const(0));
|
||||||
cell->setParam(ID(RESET_TO_MAX), RTLIL::Const(0));
|
cell->setParam(ID(RESET_TO_MAX), RTLIL::Const(0));
|
||||||
cell->setParam(ID(DIRECTION), RTLIL::Const("DOWN"));
|
cell->setParam(ID(DIRECTION), RTLIL::Const("DOWN"));
|
||||||
cell->setPort(ID(CE), RTLIL::Const(1));
|
|
||||||
cell->setPort(ID(UP), RTLIL::Const(0));
|
cell->setPort(ID(UP), RTLIL::Const(0));
|
||||||
|
|
||||||
//Hook up any parallel outputs
|
//Hook up any parallel outputs
|
||||||
|
|
Loading…
Reference in New Issue