mirror of https://github.com/YosysHQ/yosys.git
Added "write_aiger -zinit -symbols -vmap"
This commit is contained in:
Clifford Wolf
parent
c1f762ca56
commit
5fa1fa1e6f
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@ -58,6 +58,13 @@ struct AigerWriter
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dict<SigBit, int> init_inputs;
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int initstate_ff = 0;
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int mkgate(int a0, int a1)
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{
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aig_m++, aig_a++;
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aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
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return 2*aig_m;
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}
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int bit2aig(SigBit bit)
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{
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if (aig_map.count(bit) == 0)
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@ -76,9 +83,7 @@ struct AigerWriter
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auto args = and_map.at(bit);
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int a0 = bit2aig(args.first);
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int a1 = bit2aig(args.second);
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aig_m++, aig_a++;
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aig_map[bit] = 2*aig_m;
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aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
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aig_map[bit] = mkgate(a0, a1);
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}
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}
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@ -94,7 +99,8 @@ struct AigerWriter
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SigSpec initsig = sigmap(wire);
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Const initval = wire->attributes.at("\\init");
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for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
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init_map[initsig[i]] = initval[i];
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if (initval[i] == State::S0 || initval[i] == State::S1)
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init_map[initsig[i]] = initval[i] == State::S1;
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}
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if (wire->port_input)
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@ -171,7 +177,7 @@ struct AigerWriter
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for (auto it : ff_map) {
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aig_m++, aig_l++;
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aig_map[it.first] = 2*aig_m;
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ordered_latches[it.first] = aig_l;
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ordered_latches[it.first] = aig_l-1;
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if (init_map.count(it.first) == 0)
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aig_latchinit.push_back(2);
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else
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@ -184,20 +190,44 @@ struct AigerWriter
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aig_latchinit.push_back(0);
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}
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for (auto it : ff_map)
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aig_latchin.push_back(bit2aig(it.second));
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if (zinit_mode)
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{
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for (auto it : ff_map)
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{
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int l = ordered_latches[it.first];
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if (aig_latchinit.at(l) == 1)
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aig_map[it.first] ^= 1;
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if (aig_latchinit.at(l) == 2)
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{
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int gated_ffout = mkgate(aig_map[it.first], initstate_ff^1);
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int gated_initin = mkgate(init_inputs[it.first], initstate_ff);
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aig_map[it.first] = mkgate(gated_ffout^1, gated_initin^1)^1;
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}
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}
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}
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for (auto it : ff_map) {
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int a = bit2aig(it.second);
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int l = ordered_latches[it.first];
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if (zinit_mode && aig_latchinit.at(l) == 1)
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aig_latchin.push_back(a ^ 1);
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else
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aig_latchin.push_back(a);
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}
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if (!initstate_bits.empty() || !init_inputs.empty())
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aig_latchin.push_back(1);
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for (auto bit : output_bits) {
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aig_o++;
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ordered_outputs[bit] = aig_o;
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ordered_outputs[bit] = aig_o-1;
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aig_outputs.push_back(bit2aig(bit));
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}
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}
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void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode)
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void write_aiger(std::ostream &f, bool ascii_mode, bool miter_mode, bool symbols_mode)
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{
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log_assert(aig_m == aig_i + aig_l + aig_a);
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log_assert(aig_l == GetSize(aig_latchin));
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@ -215,7 +245,7 @@ struct AigerWriter
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f << stringf("%d\n", 2*i+2);
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for (int i = 0; i < aig_l; i++) {
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if (aig_latchinit.at(i) == 0)
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if (zinit_mode || aig_latchinit.at(i) == 0)
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f << stringf("%d %d\n", 2*(aig_i+i)+2, aig_latchin.at(i));
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else if (aig_latchinit.at(i) == 1)
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f << stringf("%d %d 1\n", 2*(aig_i+i)+2, aig_latchin.at(i));
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@ -232,7 +262,7 @@ struct AigerWriter
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else
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{
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for (int i = 0; i < aig_l; i++) {
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if (aig_latchinit.at(i) == 0)
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if (zinit_mode || aig_latchinit.at(i) == 0)
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f << stringf("%d\n", aig_latchin.at(i));
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else if (aig_latchinit.at(i) == 1)
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f << stringf("%d 1\n", aig_latchin.at(i));
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@ -254,19 +284,69 @@ struct AigerWriter
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}
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}
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if (symbols_mode)
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{
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for (auto wire : module->wires())
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{
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if (wire->name[0] == '$')
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continue;
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SigSpec sig = sigmap(wire);
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for (int i = 0; i < GetSize(wire); i++)
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{
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if (wire->port_input) {
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int a = aig_map.at(sig[i]);
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log_assert((a & 1) == 0);
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if (GetSize(wire) != 1)
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f << stringf("i%d %s[%d]\n", (a >> 1)-1, log_id(wire), i);
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else
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f << stringf("i%d %s\n", (a >> 1)-1, log_id(wire));
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}
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if (wire->port_output) {
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int o = ordered_outputs.at(sig[i]);
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if (GetSize(wire) != 1)
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f << stringf("%c%d %s[%d]\n", miter_mode ? 'b' : 'o', o, log_id(wire), i);
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else
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f << stringf("%c%d %s\n", miter_mode ? 'b' : 'o', o, log_id(wire));
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}
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if (init_inputs.count(sig[i])) {
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int a = init_inputs.at(sig[i]);
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log_assert((a & 1) == 0);
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if (GetSize(wire) != 1)
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f << stringf("i%d init:%s[%d]\n", (a >> 1)-1, log_id(wire), i);
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else
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f << stringf("i%d init:%s\n", (a >> 1)-1, log_id(wire));
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}
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if (ordered_latches.count(sig[i])) {
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int l = ordered_latches.at(sig[i]);
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const char *p = (zinit_mode && (aig_latchinit.at(l) == 1)) ? "!" : "";
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if (GetSize(wire) != 1)
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f << stringf("l%d %s%s[%d]\n", l, p, log_id(wire), i);
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else
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f << stringf("l%d %s%s\n", l, p, log_id(wire));
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}
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}
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}
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}
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f << stringf("c\nGenerated by %s\n", yosys_version_str);
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}
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void write_map(std::ostream &f)
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void write_map(std::ostream &f, bool verbose_map)
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{
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dict<int, string> input_lines;
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dict<int, string> init_lines;
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dict<int, string> output_lines;
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dict<int, string> latch_lines;
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dict<int, string> wire_lines;
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for (auto wire : module->wires())
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{
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if (wire->name[0] == '$')
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if (!verbose_map && wire->name[0] == '$')
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continue;
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SigSpec sig = sigmap(wire);
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@ -277,21 +357,32 @@ struct AigerWriter
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continue;
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int a = aig_map.at(sig[i]);
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// wire_lines[a] = stringf("wire %d %d %s\n", a, i, log_id(wire));
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if (verbose_map)
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wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
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if (wire->port_input) {
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log_assert((a & 1) == 0);
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input_lines[a] = stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
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input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
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}
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if (wire->port_output) {
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int n = ordered_outputs.at(sig[i]);
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output_lines[n] = stringf("output %d %d %s\n", n-1, i, log_id(wire));
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int o = ordered_outputs.at(sig[i]);
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output_lines[o] += stringf("output %d %d %s\n", o, i, log_id(wire));
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}
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if (init_inputs.count(sig[i])) {
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int a = init_inputs.at(sig[i]);
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log_assert((a & 1) == 0);
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init_lines[a] += stringf("init %d %d %s\n", (a >> 1)-1, i, log_id(wire));
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}
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if (ordered_latches.count(sig[i])) {
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int n = ordered_latches.at(sig[i]);
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latch_lines[n] = stringf("latch %d %d %s\n", n-1, i, log_id(wire));
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int l = ordered_latches.at(sig[i]);
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if (zinit_mode && (aig_latchinit.at(l) == 1))
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latch_lines[l] += stringf("invlatch %d %d %s\n", l, i, log_id(wire));
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else
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latch_lines[l] += stringf("latch %d %d %s\n", l, i, log_id(wire));
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}
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}
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}
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@ -300,6 +391,10 @@ struct AigerWriter
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for (auto &it : input_lines)
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f << it.second;
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init_lines.sort();
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for (auto &it : init_lines)
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f << it.second;
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output_lines.sort();
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for (auto &it : output_lines)
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f << it.second;
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@ -328,15 +423,21 @@ struct AigerBackend : public Backend {
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log(" -ascii\n");
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log(" write ASCII version of AGIER format\n");
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log("\n");
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// log(" -zinit\n");
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// log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
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// log(" uninitialized FFs.\n");
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// log("\n");
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log(" -zinit\n");
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log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
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log(" uninitialized FFs.\n");
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log("\n");
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log(" -miter\n");
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log(" design outputs are AIGER bad state properties\n");
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log("\n");
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log(" -symbols\n");
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log(" include a symbol table in the generated AIGER file\n");
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log("\n");
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log(" -map <filename>\n");
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log(" write an extra file with port, latch and wire mappings\n");
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log(" write an extra file with port and latch symbols\n");
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log("\n");
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log(" -vmap <filename>\n");
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log(" like -map, but more verbose\n");
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log("\n");
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}
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virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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@ -344,6 +445,8 @@ struct AigerBackend : public Backend {
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bool ascii_mode = false;
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bool zinit_mode = false;
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bool miter_mode = false;
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bool symbols_mode = false;
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bool verbose_map = false;
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std::string map_filename;
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log_header(design, "Executing AIGER backend.\n");
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@ -363,10 +466,19 @@ struct AigerBackend : public Backend {
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miter_mode = true;
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continue;
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}
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if (args[argidx] == "-map" && argidx+1 < args.size()) {
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if (args[argidx] == "-symbols") {
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symbols_mode = true;
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continue;
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}
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if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
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map_filename = args[++argidx];
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continue;
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}
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if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) {
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map_filename = args[++argidx];
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verbose_map = true;
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continue;
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}
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break;
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}
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extra_args(f, filename, args, argidx);
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@ -376,18 +488,15 @@ struct AigerBackend : public Backend {
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if (top_module == nullptr)
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log_error("Can't find top module in current design!\n");
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if (zinit_mode)
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log_error("zinit mode is not implemented yet.\n");
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AigerWriter writer(top_module, zinit_mode);
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writer.write_aiger(*f, ascii_mode, miter_mode);
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writer.write_aiger(*f, ascii_mode, miter_mode, symbols_mode);
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if (!map_filename.empty()) {
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std::ofstream mapf;
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mapf.open(map_filename.c_str(), std::ofstream::trunc);
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if (mapf.fail())
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log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
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writer.write_map(mapf);
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writer.write_map(mapf, verbose_map);
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}
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}
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} AigerBackend;
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