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Merge pull request #4042 from YosysHQ/verific_cell 

Verific: Add attributes to module instantiation
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Miodrag Milanović 2023-11-23 11:38:01 +01:00 committed by GitHub
parent c95298225d 8f207eed1b
commit 5e603c2241
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frontends/verific/verific.cc
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@ -1980,6 +1980,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
}
RTLIL::Cell *cell = module->addCell(inst_name, inst_type);
import_attributes(cell->attributes, inst);
if (inst->IsPrimitive() && mode_keep)
cell->attributes[ID::keep] = 1;