From 8f207eed1baf85ad185c7139729b10f9756a0041 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Thu, 23 Nov 2023 11:01:49 +0100
Subject: [PATCH] Add attributes to module instantiation

---
 frontends/verific/verific.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 9737fde89..ce687601f 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1980,6 +1980,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		}
 
 		RTLIL::Cell *cell = module->addCell(inst_name, inst_type);
+		import_attributes(cell->attributes, inst);
 
 		if (inst->IsPrimitive() && mode_keep)
 			cell->attributes[ID::keep] = 1;