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Merge pull request #3777 from YosysHQ/micko/vhdl_verific 

Fix importing parametrized VHDL entity
This commit is contained in:
Miodrag Milanović 2023-05-23 11:44:49 +02:00 committed by GitHub
parent 4f3d1be96a ecd289c100
commit 5e36effe3c
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 4 additions and 1 deletions
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5
frontends/verific/verific.cc
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@ -2468,6 +2468,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
Netlist *nl;
int i;
std::string cell_name = top;
FOREACH_ARRAY_ITEM(netlists, i, nl) {
if (!nl) continue;
@ -2475,7 +2476,9 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
continue;
nl->AddAtt(new Att(" \\top", NULL));
nl_todo.emplace(nl->CellBaseName(), nl);
cell_name = nl->Owner()->Name();
}
if (top.empty()) cell_name = top;
delete netlists;
@ -2495,7 +2498,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
if (nl_done.count(it->first) == 0) {
VerificImporter importer(false, false, false, false, false, false, false);
nl_done[it->first] = it->second;
importer.import_netlist(design, nl, nl_todo, nl->Owner()->Name() == top);
importer.import_netlist(design, nl, nl_todo, nl->Owner()->Name() == cell_name);
}
nl_todo.erase(it);
}