mirror of https://github.com/YosysHQ/yosys.git
Revert "Trim shiftx_width when upper bits are 1'bx"
This reverts commit 7e7965ca7b
.
This commit is contained in:
parent
c7859531c2
commit
5c8344363f
|
@ -164,11 +164,6 @@ endmatch
|
||||||
|
|
||||||
code shiftx_width
|
code shiftx_width
|
||||||
shiftx_width = param(shiftx, \A_WIDTH).as_int();
|
shiftx_width = param(shiftx, \A_WIDTH).as_int();
|
||||||
while (shiftx_width > 1) {
|
|
||||||
if (port(shiftx, \A)[shiftx_width-1] != State::Sx)
|
|
||||||
break;
|
|
||||||
--shiftx_width;
|
|
||||||
}
|
|
||||||
endcode
|
endcode
|
||||||
|
|
||||||
match first
|
match first
|
||||||
|
@ -182,7 +177,7 @@ code
|
||||||
chain.push_back(first);
|
chain.push_back(first);
|
||||||
subpattern(tail);
|
subpattern(tail);
|
||||||
finally
|
finally
|
||||||
if (GetSize(chain) == shiftx_width)
|
if (GetSize(chain) == param(shiftx, \A_WIDTH).as_int())
|
||||||
accept;
|
accept;
|
||||||
chain.clear();
|
chain.clear();
|
||||||
endcode
|
endcode
|
||||||
|
|
Loading…
Reference in New Issue