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Merge pull request #4720 from georgerennie/george/bufnorm_constants 

bufnorm: preserve constant bits driving wires
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Martin Povišer 2024-11-07 13:56:53 +01:00 committed by GitHub
parent 2de9f00368 a31c968340
commit 5c1889634d
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GPG Key ID: B5690EEEBB952194
2 changed files with 18 additions and 2 deletions
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9
passes/techmap/bufnorm.cc
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@ -438,8 +438,13 @@ struct BufnormPass : public Pass {
bool chain_this_wire = chain_this_wire_f(wire);
SigSpec keysig = sigmap(wire), insig = wire, outsig = wire;
for (int i = 0; i < GetSize(insig); i++)
insig[i] = mapped_bits.at(keysig[i], State::Sx);
for (int i = 0; i < GetSize(insig); i++) {
if (keysig[i].is_wire())
insig[i] = mapped_bits.at(keysig[i], State::Sx);
else
insig[i] = keysig[i];
}
if (chain_this_wire) {
for (int i = 0; i < GetSize(outsig); i++)
mapped_bits[keysig[i]] = outsig[i];

11
tests/techmap/bufnorm.ys Normal file
View File

@ -0,0 +1,11 @@
# Check wires driven by constants are kept
read_verilog <<EOT
module top(output wire [7:0] y);
assign y = 27;
endmodule
EOT
equiv_opt -assert bufnorm
design -load postopt
select -assert-count 1 t:$buf
select -assert-count 1 w:y %ci t:$buf %i