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Docs: Apply verific docs suggestions

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Krystine Sherwin 2024-08-23 09:23:57 +12:00
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5
docs/source/using_yosys/more_scripting/load_design.rst
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@ -30,8 +30,9 @@ keyword: Frontends
.. note:: .. note::
The Verific frontend for Yosys, which provides the :cmd:ref:`verific` The Verific frontend for Yosys, which provides the :cmd:ref:`verific`
command, requires Yosys to be built with Verific. This is not the same as command, requires Yosys to be built with Verific. For full functionality,
simply having a Verific license when using Yosys. Check custom modifications to the Verific source code from YosysHQ are required,
but limited useability can be achieved with some stock Verific builds. Check
:doc:`/yosys_internals/extending_yosys/build_verific` for more. :doc:`/yosys_internals/extending_yosys/build_verific` for more.
Others: Others:

4
docs/source/using_yosys/synthesis/memory.rst
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@ -697,8 +697,8 @@ TDP with multiple read ports
Patterns only supported with Verific Patterns only supported with Verific
------------------------------------ ------------------------------------
The following patterns are only supported when Yosys is built with the Verific The following patterns are only supported when the design is read in using the
front-end. Verific front-end.
Synchronous SDP with write-first behavior via blocking assignments Synchronous SDP with write-first behavior via blocking assignments
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

17
docs/source/yosys_internals/extending_yosys/build_verific.rst
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@ -33,9 +33,8 @@ incorrect results.
.. note:: .. note::
Some of the formal verification front-end tools may not be fully supported Some of the formal verification front-end tools may not be fully supported
without the full TabbyCAD suite. If you are wanting to use these tools, without the full TabbyCAD suite. If you want to use these tools, including
including SBY, make sure to ask us if the Yosys-Verific patch is right for SBY, make sure to ask us if the Yosys-Verific patch is right for you.
you.
Compile options Compile options
--------------- ---------------
@ -123,6 +122,12 @@ lists a series of build configurations which are possible, but only provide a
limited subset of features. Please note that support is limited without YosysHQ limited subset of features. Please note that support is limited without YosysHQ
specific extensions of Verific library. specific extensions of Verific library.
Configuration values:
a. ``ENABLE_VERIFIC_SYSTEMVERILOG``
b. ``ENABLE_VERIFIC_VHDL``
c. ``ENABLE_VERIFIC_HIER_TREE``
d. ``ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS``
+--------------------------------------------------------------------------+-----+-----+-----+-----+ +--------------------------------------------------------------------------+-----+-----+-----+-----+
| | Configuration values | | | Configuration values |
+--------------------------------------------------------------------------+-----+-----+-----+-----+ +--------------------------------------------------------------------------+-----+-----+-----+-----+
@ -141,12 +146,6 @@ specific extensions of Verific library.
| SystemVerilog + VHDL + RTL elaboration + Static elaboration + Hier tree | 1 | 1 | 1 | 0 | | SystemVerilog + VHDL + RTL elaboration + Static elaboration + Hier tree | 1 | 1 | 1 | 0 |
+--------------------------------------------------------------------------+-----+-----+-----+-----+ +--------------------------------------------------------------------------+-----+-----+-----+-----+
Configuration values:
a. ``ENABLE_VERIFIC_SYSTEMVERILOG``
b. ``ENABLE_VERIFIC_VHDL``
c. ``ENABLE_VERIFIC_HIER_TREE``
d. ``ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS``
.. note:: .. note::
In case your Verific build has EDIF and/or Liberty support, you can enable In case your Verific build has EDIF and/or Liberty support, you can enable