From 583d820dc2cd1ef9e385145452550ab71be9115f Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Fri, 23 Aug 2024 09:23:57 +1200
Subject: [PATCH] Docs: Apply verific docs suggestions

---
 .../using_yosys/more_scripting/load_design.rst  |  5 +++--
 docs/source/using_yosys/synthesis/memory.rst    |  4 ++--
 .../extending_yosys/build_verific.rst           | 17 ++++++++---------
 3 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/docs/source/using_yosys/more_scripting/load_design.rst b/docs/source/using_yosys/more_scripting/load_design.rst
index cf6a1dc1f..bbc55a36b 100644
--- a/docs/source/using_yosys/more_scripting/load_design.rst
+++ b/docs/source/using_yosys/more_scripting/load_design.rst
@@ -30,8 +30,9 @@ keyword: Frontends
 .. note::
 
    The Verific frontend for Yosys, which provides the :cmd:ref:`verific`
-   command, requires Yosys to be built with Verific.  This is not the same as
-   simply having a Verific license when using Yosys.  Check
+   command, requires Yosys to be built with Verific.  For full functionality,
+   custom modifications to the Verific source code from YosysHQ are required,
+   but limited useability can be achieved with some stock Verific builds.  Check
    :doc:`/yosys_internals/extending_yosys/build_verific` for more.
 
 Others:
diff --git a/docs/source/using_yosys/synthesis/memory.rst b/docs/source/using_yosys/synthesis/memory.rst
index 8306c82b9..e95a64875 100644
--- a/docs/source/using_yosys/synthesis/memory.rst
+++ b/docs/source/using_yosys/synthesis/memory.rst
@@ -697,8 +697,8 @@ TDP with multiple read ports
 Patterns only supported with Verific
 ------------------------------------
 
-The following patterns are only supported when Yosys is built with the Verific
-front-end.
+The following patterns are only supported when the design is read in using the
+Verific front-end.
 
 Synchronous SDP with write-first behavior via blocking assignments
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/source/yosys_internals/extending_yosys/build_verific.rst b/docs/source/yosys_internals/extending_yosys/build_verific.rst
index ae9e4f1d4..b20517bd3 100644
--- a/docs/source/yosys_internals/extending_yosys/build_verific.rst
+++ b/docs/source/yosys_internals/extending_yosys/build_verific.rst
@@ -33,9 +33,8 @@ incorrect results.
 .. note::
 
    Some of the formal verification front-end tools may not be fully supported
-   without the full TabbyCAD suite.  If you are wanting to use these tools,
-   including SBY, make sure to ask us if the Yosys-Verific patch is right for
-   you.
+   without the full TabbyCAD suite.  If you want to use these tools, including
+   SBY, make sure to ask us if the Yosys-Verific patch is right for you.
 
 Compile options
 ---------------
@@ -123,6 +122,12 @@ lists a series of build configurations which are possible, but only provide a
 limited subset of features.  Please note that support is limited without YosysHQ
 specific extensions of Verific library.
 
+Configuration values:
+  a. ``ENABLE_VERIFIC_SYSTEMVERILOG``
+  b. ``ENABLE_VERIFIC_VHDL``
+  c. ``ENABLE_VERIFIC_HIER_TREE``
+  d. ``ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS``
+
 +--------------------------------------------------------------------------+-----+-----+-----+-----+
 |                                                                          | Configuration values  |
 +--------------------------------------------------------------------------+-----+-----+-----+-----+
@@ -141,12 +146,6 @@ specific extensions of Verific library.
 | SystemVerilog + VHDL + RTL elaboration + Static elaboration + Hier tree  |   1 |   1 |   1 |   0 |
 +--------------------------------------------------------------------------+-----+-----+-----+-----+
 
-Configuration values:
-  a. ``ENABLE_VERIFIC_SYSTEMVERILOG``
-  b. ``ENABLE_VERIFIC_VHDL``
-  c. ``ENABLE_VERIFIC_HIER_TREE``
-  d. ``ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS``
-
 .. note::
 
    In case your Verific build has EDIF and/or Liberty support, you can enable