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Merge pull request #2057 from YosysHQ/eddie/fix_task_attr 

verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
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Eddie Hung 2020-05-21 11:00:36 -07:00 committed by GitHub
parent 637650597b 38e858af8d
commit 574812d9a5
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2 changed files with 37 additions and 11 deletions
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20
frontends/verilog/verilog_parser.y
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@ -2228,24 +2228,24 @@ simple_behavioral_stmt:
behavioral_stmt: behavioral_stmt:
defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl | defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl |
non_opt_delay behavioral_stmt | non_opt_delay behavioral_stmt |
simple_behavioral_stmt ';' | ';' | attr simple_behavioral_stmt ';' | ';' |
hierarchical_id attr { attr hierarchical_id {
AstNode *node = new AstNode(AST_TCALL); AstNode *node = new AstNode(AST_TCALL);
node->str = *$1; node->str = *$2;
delete $1; delete $2;
ast_stack.back()->children.push_back(node); ast_stack.back()->children.push_back(node);
ast_stack.push_back(node); ast_stack.push_back(node);
append_attr(node, $2); append_attr(node, $1);
} opt_arg_list ';'{ } opt_arg_list ';'{
ast_stack.pop_back(); ast_stack.pop_back();
} | } |
TOK_MSG_TASKS attr { attr TOK_MSG_TASKS {
AstNode *node = new AstNode(AST_TCALL); AstNode *node = new AstNode(AST_TCALL);
node->str = *$1; node->str = *$2;
delete $1; delete $2;
ast_stack.back()->children.push_back(node); ast_stack.back()->children.push_back(node);
ast_stack.push_back(node); ast_stack.push_back(node);
append_attr(node, $2); append_attr(node, $1);
} opt_arg_list ';'{ } opt_arg_list ';'{
ast_stack.pop_back(); ast_stack.pop_back();
} | } |
@ -2342,8 +2342,6 @@ behavioral_stmt:
ast_stack.pop_back(); ast_stack.pop_back();
}; };
;
unique_case_attr: unique_case_attr:
/* empty */ { /* empty */ {
$$ = false; $$ = false;

28
tests/verilog/task_attr.ys Normal file
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@ -0,0 +1,28 @@
read_verilog <<EOT
module top;
task foo;
endtask
always @*
(* foo *) foo;
initial
if (0) $info("bar");
endmodule
EOT
# Since task enables are not an RTLIL object,
# any attributes on their AST get dropped
select -assert-none a:* a:src %d
logger -expect error "syntax error, unexpected ATTR_BEGIN" 1
design -reset
read_verilog <<EOT
module top;
task foo;
endtask
always @*
foo (* foo *);
endmodule
EOT