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Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp

This commit is contained in:
Eddie Hung 2019-07-16 14:18:36 -07:00
parent 9616dbd125 d38df68d26
commit 569cd66764
4 changed files with 35 additions and 27 deletions
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38
techlibs/common/mul2dsp.v
View File

@ -80,19 +80,21 @@ module \$__mul_gen (A, B, Y);
localparam n = n_floored + (n_floored*`DSP_A_MAXWIDTH < A_WIDTH ? 1 : 0); localparam n = n_floored + (n_floored*`DSP_A_MAXWIDTH < A_WIDTH ? 1 : 0);
wire [`DSP_A_MAXWIDTH+B_WIDTH-1:0] partial [n-1:1]; wire [`DSP_A_MAXWIDTH+B_WIDTH-1:0] partial [n-1:1];
wire [Y_WIDTH-1:0] partial_sum [n-2:0]; wire [Y_WIDTH-1:0] partial_sum [n-2:0];
localparam int_yw = `MIN(Y_WIDTH, B_WIDTH+`DSP_A_MAXWIDTH);
\$__mul_gen #( \$__mul_gen #(
.A_SIGNED(A_SIGNED), .A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(`DSP_A_MAXWIDTH), .A_WIDTH(`DSP_A_MAXWIDTH),
.B_WIDTH(B_WIDTH), .B_WIDTH(B_WIDTH),
.Y_WIDTH(B_WIDTH+`DSP_A_MAXWIDTH) .Y_WIDTH(int_yw)
) mul_slice_first ( ) mul_slice_first (
.A(A[`DSP_A_MAXWIDTH-1:0]), .A(A[`DSP_A_MAXWIDTH-1:0]),
.B(B), .B(B),
.Y(partial_sum[0][B_WIDTH+`DSP_A_MAXWIDTH-1:0]) .Y(partial_sum[0][int_yw-1:0])
); );
assign partial_sum[0][Y_WIDTH-1:B_WIDTH+`DSP_A_MAXWIDTH]=0; if (Y_WIDTH > int_yw)
assign partial_sum[0][Y_WIDTH-1:int_yw]=0;
for (i = 1; i < n-1; i=i+1) begin:slice for (i = 1; i < n-1; i=i+1) begin:slice
\$__mul_gen #( \$__mul_gen #(
@ -100,15 +102,15 @@ module \$__mul_gen (A, B, Y);
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(`DSP_A_MAXWIDTH), .A_WIDTH(`DSP_A_MAXWIDTH),
.B_WIDTH(B_WIDTH), .B_WIDTH(B_WIDTH),
.Y_WIDTH(B_WIDTH+`DSP_A_MAXWIDTH) .Y_WIDTH(int_yw)
) mul_slice ( ) mul_slice (
.A(A[(i+1)*`DSP_A_MAXWIDTH-1:i*`DSP_A_MAXWIDTH]), .A(A[(i+1)*`DSP_A_MAXWIDTH-1:i*`DSP_A_MAXWIDTH]),
.B(B), .B(B),
.Y(partial[i][B_WIDTH+`DSP_A_MAXWIDTH-1:0]) .Y(partial[i][int_yw-1:0])
); );
//assign partial_sum[i] = (partial[i] << i*`DSP_A_MAXWIDTH) + partial_sum[i-1]; //assign partial_sum[i] = (partial[i] << i*`DSP_A_MAXWIDTH) + partial_sum[i-1];
assign partial_sum[i] = { assign partial_sum[i] = {
partial[i][B_WIDTH+`DSP_A_MAXWIDTH-1:0] partial[i][int_yw-1:0]
+ partial_sum[i-1][Y_WIDTH-1:(i*`DSP_A_MAXWIDTH)], + partial_sum[i-1][Y_WIDTH-1:(i*`DSP_A_MAXWIDTH)],
partial_sum[i-1][(i*`DSP_A_MAXWIDTH)-1:0] partial_sum[i-1][(i*`DSP_A_MAXWIDTH)-1:0]
}; };
@ -119,15 +121,15 @@ module \$__mul_gen (A, B, Y);
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH), .A_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH),
.B_WIDTH(B_WIDTH), .B_WIDTH(B_WIDTH),
.Y_WIDTH(A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH), .Y_WIDTH(`MIN(Y_WIDTH, A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH)),
) mul_slice_last ( ) mul_slice_last (
.A(A[A_WIDTH-1:(n-1)*`DSP_A_MAXWIDTH]), .A(A[A_WIDTH-1:(n-1)*`DSP_A_MAXWIDTH]),
.B(B), .B(B),
.Y(partial[n-1][A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH-1:0]) .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH)-1:0])
); );
//assign Y = (partial[n-1] << (n-1)*`DSP_A_MAXWIDTH) + partial_sum[n-2]; //assign Y = (partial[n-1] << (n-1)*`DSP_A_MAXWIDTH) + partial_sum[n-2];
assign Y = { assign Y = {
partial[n-1][A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH:0] partial[n-1][`MIN(Y_WIDTH, A_WIDTH-(n-1)*`DSP_A_MAXWIDTH+B_WIDTH):0]
+ partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_A_MAXWIDTH)], + partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_A_MAXWIDTH)],
partial_sum[n-2][((n-1)*`DSP_A_MAXWIDTH)-1:0] partial_sum[n-2][((n-1)*`DSP_A_MAXWIDTH)-1:0]
}; };
@ -137,18 +139,20 @@ module \$__mul_gen (A, B, Y);
localparam n = n_floored + (n_floored*`DSP_B_MAXWIDTH < B_WIDTH ? 1 : 0); localparam n = n_floored + (n_floored*`DSP_B_MAXWIDTH < B_WIDTH ? 1 : 0);
wire [A_WIDTH+`DSP_B_MAXWIDTH-1:0] partial [n-1:1]; wire [A_WIDTH+`DSP_B_MAXWIDTH-1:0] partial [n-1:1];
wire [Y_WIDTH-1:0] partial_sum [n-2:0]; wire [Y_WIDTH-1:0] partial_sum [n-2:0];
localparam int_yw = `MIN(Y_WIDTH, A_WIDTH+`DSP_B_MAXWIDTH);
\$__mul_gen #( \$__mul_gen #(
.A_SIGNED(A_SIGNED), .A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH), .A_WIDTH(A_WIDTH),
.B_WIDTH(`DSP_B_MAXWIDTH), .B_WIDTH(`DSP_B_MAXWIDTH),
.Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH) .Y_WIDTH(int_yw)
) mul_first ( ) mul_first (
.A(A), .A(A),
.B(B[`DSP_B_MAXWIDTH-1:0]), .B(B[`DSP_B_MAXWIDTH-1:0]),
.Y(partial_sum[0][A_WIDTH+`DSP_B_MAXWIDTH-1:0]) .Y(partial_sum[0][int_yw-1:0])
); );
if (Y_WIDTH > int_yw)
assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0; assign partial_sum[0][Y_WIDTH-1:A_WIDTH+`DSP_B_MAXWIDTH]=0;
for (i = 1; i < n-1; i=i+1) begin:slice for (i = 1; i < n-1; i=i+1) begin:slice
@ -157,11 +161,11 @@ module \$__mul_gen (A, B, Y);
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH), .A_WIDTH(A_WIDTH),
.B_WIDTH(`DSP_B_MAXWIDTH), .B_WIDTH(`DSP_B_MAXWIDTH),
.Y_WIDTH(A_WIDTH+`DSP_B_MAXWIDTH) .Y_WIDTH(int_yw)
) mul ( ) mul (
.A(A), .A(A),
.B(B[(i+1)*`DSP_B_MAXWIDTH-1:i*`DSP_B_MAXWIDTH]), .B(B[(i+1)*`DSP_B_MAXWIDTH-1:i*`DSP_B_MAXWIDTH]),
.Y(partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:0]) .Y(partial[i][int_yw-1:0])
); );
//assign partial_sum[i] = (partial[i] << i*`DSP_B_MAXWIDTH) + partial_sum[i-1]; //assign partial_sum[i] = (partial[i] << i*`DSP_B_MAXWIDTH) + partial_sum[i-1];
// was: // was:
@ -170,7 +174,7 @@ module \$__mul_gen (A, B, Y);
// partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)], // partial[i][`DSP_B_MAXWIDTH-1:0] + partial_sum[i-1][A_WIDTH+(i*`DSP_B_MAXWIDTH)-1:A_WIDTH+((i-1)*`DSP_B_MAXWIDTH)],
// partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0] // partial_sum[i-1][A_WIDTH+((i-1)*`DSP_B_MAXWIDTH):0]
assign partial_sum[i] = { assign partial_sum[i] = {
partial[i][A_WIDTH+`DSP_B_MAXWIDTH-1:0] partial[i][int_yw-1:0]
+ partial_sum[i-1][Y_WIDTH-1:(i*`DSP_B_MAXWIDTH)], + partial_sum[i-1][Y_WIDTH-1:(i*`DSP_B_MAXWIDTH)],
partial_sum[i-1][(i*`DSP_B_MAXWIDTH)-1:0] partial_sum[i-1][(i*`DSP_B_MAXWIDTH)-1:0]
}; };
@ -181,11 +185,11 @@ module \$__mul_gen (A, B, Y);
.B_SIGNED(B_SIGNED), .B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH), .A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH-(n-1)*`DSP_B_MAXWIDTH), .B_WIDTH(B_WIDTH-(n-1)*`DSP_B_MAXWIDTH),
.Y_WIDTH(A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH) .Y_WIDTH(`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH))
) mul_last ( ) mul_last (
.A(A), .A(A),
.B(B[B_WIDTH-1:(n-1)*`DSP_B_MAXWIDTH]), .B(B[B_WIDTH-1:(n-1)*`DSP_B_MAXWIDTH]),
.Y(partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0]) .Y(partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH)-1:0])
); );
// AMD: this came comment out -- looks closer to right answer // AMD: this came comment out -- looks closer to right answer
//assign Y = (partial[n-1] << (n-1)*`DSP_B_MAXWIDTH) + partial_sum[n-2]; //assign Y = (partial[n-1] << (n-1)*`DSP_B_MAXWIDTH) + partial_sum[n-2];
@ -195,7 +199,7 @@ module \$__mul_gen (A, B, Y);
// partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)], // partial[n-1][`DSP_B_MAXWIDTH-1:0] + partial_sum[n-2][A_WIDTH+((n-1)*`DSP_B_MAXWIDTH)-1:A_WIDTH+((n-2)*`DSP_B_MAXWIDTH)],
// partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0] // partial_sum[n-2][A_WIDTH+((n-2)*`DSP_B_MAXWIDTH):0]
assign Y = { assign Y = {
partial[n-1][A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH-1:0] partial[n-1][`MIN(Y_WIDTH, A_WIDTH+B_WIDTH-(n-1)*`DSP_B_MAXWIDTH)-1:0]
+ partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_B_MAXWIDTH)], + partial_sum[n-2][Y_WIDTH-1:((n-1)*`DSP_B_MAXWIDTH)],
partial_sum[n-2][((n-1)*`DSP_B_MAXWIDTH)-1:0] partial_sum[n-2][((n-1)*`DSP_B_MAXWIDTH)-1:0]
}; };

2
techlibs/xilinx/cells_sim.v
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@ -516,7 +516,7 @@ module DSP48E1 (
if (PCIN != 48'b0) $fatal(1, "Unsupported PCIN value"); if (PCIN != 48'b0) $fatal(1, "Unsupported PCIN value");
if (CARRYIN != 1'b0) $fatal(1, "Unsupported CARRYIN value"); if (CARRYIN != 1'b0) $fatal(1, "Unsupported CARRYIN value");
`endif `endif
Pr[42:0] <= Ar[24:0] * Br; Pr[42:0] <= $signed(Ar[24:0]) * $signed(Br);
end end
generate generate

6
techlibs/xilinx/dsp_map.v
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@ -1,4 +1,4 @@
module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); module \$__MUL25X18 (input [23:0] A, input [16:0] B, output [40:0] Y);
wire [47:0] P_48; wire [47:0] P_48;
DSP48E1 #( DSP48E1 #(
// Disable all registers // Disable all registers
@ -20,8 +20,8 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
.PREG(0) .PREG(0)
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
//Data path //Data path
.A({5'b0, A}), .A({6'b0, A}),
.B(B), .B({1'b0, B}),
.C(48'b0), .C(48'b0),
.D(24'b0), .D(24'b0),
.P(P_48), .P(P_48),

6
techlibs/xilinx/synth_xilinx.cc
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@ -284,8 +284,12 @@ struct SynthXilinxPass : public ScriptPass
run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6"); run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6");
// The actual behaviour of the Xilinx DSP is a signed 25x18 multiply
// Due to current limitations of mul2dsp, we are actually mapping as a 24x17
// unsigned multiply with MSBs set to 1'b0
if (!nodsp || help_mode) if (!nodsp || help_mode)
run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 -D DSP_NAME=$__MUL25X18"); run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=24 -D DSP_B_MAXWIDTH=17 -D DSP_NAME=$__MUL25X18");
run("alumacc"); run("alumacc");
run("share"); run("share");