mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #4583 from YosysHQ/emil/clock_gate
clockgate: centralize clock enables out of FFs
This commit is contained in:
Emil J
GitHub
commit
52382c6544
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@ -49,6 +49,7 @@ OBJS += passes/techmap/dffunmap.o
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OBJS += passes/techmap/flowmap.o
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OBJS += passes/techmap/extractinv.o
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OBJS += passes/techmap/cellmatch.o
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OBJS += passes/techmap/clockgate.o
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endif
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ifeq ($(DISABLE_SPAWN),0)
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@ -0,0 +1,227 @@
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#include "kernel/yosys.h"
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#include "kernel/ff.h"
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#include <optional>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct ClockGateCell {
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IdString name;
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IdString ce_pin;
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IdString clk_in_pin;
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IdString clk_out_pin;
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};
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ClockGateCell icg_from_arg(std::string& name, std::string& str) {
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ClockGateCell c;
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c.name = RTLIL::escape_id(name);
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char delimiter = ':';
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size_t pos1 = str.find(delimiter);
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if (pos1 == std::string::npos)
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log_cmd_error("Not enough ports in descriptor string");
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size_t pos2 = str.find(delimiter, pos1 + 1);
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if (pos2 == std::string::npos)
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log_cmd_error("Not enough ports in descriptor string");
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size_t pos3 = str.find(delimiter, pos2 + 1);
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if (pos3 != std::string::npos)
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log_cmd_error("Too many ports in descriptor string");
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std::string ce = str.substr(0, pos1);
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c.ce_pin = RTLIL::escape_id(ce);
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std::string clk_in = str.substr(pos1 + 1, pos2 - (pos1 + 1));
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c.clk_in_pin = RTLIL::escape_id(clk_in);
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std::string clk_out = str.substr(pos2 + 1, str.size() - (pos2 + 1));
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c.clk_out_pin = RTLIL::escape_id(clk_out);
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return c;
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}
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struct ClockgatePass : public Pass {
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ClockgatePass() : Pass("clockgate", "extract clock gating out of flip flops") { }
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void help() override {
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" clockgate [options] [selection]\n");
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log("\n");
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log("This pass transforms each set of FFs sharing the same clock and\n");
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log("enable signal into a clock-gating cell and a set of enable-less FFs.\n");
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log("Primarily a power-saving transformation on ASIC designs.\n");
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log("\n");
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log(" -pos <celltype> <ce>:<clk>:<gclk>\n");
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log(" If specified, rising-edge FFs will have CE inputs\n");
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log(" removed and a gated clock will be created by the\n");
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log(" user-specified <celltype> ICG (integrated clock gating)\n");
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log(" cell with ports named <ce>, <clk>, <gclk>.\n");
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log(" The ICG's clock enable pin must be active high.\n");
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log(" -neg <celltype> <ce>:<clk>:<gclk>\n");
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log(" If specified, falling-edge FFs will have CE inputs\n");
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log(" removed and a gated clock will be created by the\n");
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log(" user-specified <celltype> ICG (integrated clock gating)\n");
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log(" cell with ports named <ce>, <clk>, <gclk>.\n");
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log(" The ICG's clock enable pin must be active high.\n");
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log(" -tie_lo <port_name>\n");
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log(" Port <port_name> of the ICG will be tied to zero.\n");
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log(" Intended for DFT scan-enable pins.\n");
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log(" -min_net_size <n>\n");
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log(" Only transform sets of at least <n> eligible FFs.\n");
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// log(" \n");
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}
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// One ICG will be generated per ClkNetInfo
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// if the number of FFs associated with it is sufficent
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struct ClkNetInfo {
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// Original, ungated clock into enabled FF
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SigBit clk_bit;
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// Original clock enable into enabled FF
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SigBit ce_bit;
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bool pol_clk;
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bool pol_ce;
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unsigned int hash() const {
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auto t = std::make_tuple(clk_bit, ce_bit, pol_clk, pol_ce);
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unsigned int h = mkhash_init;
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h = mkhash(h, hash_ops<decltype(t)>::hash(t));
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return h;
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}
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bool operator==(const ClkNetInfo& other) const {
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return (clk_bit == other.clk_bit) &&
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(ce_bit == other.ce_bit) &&
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(pol_clk == other.pol_clk) &&
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(pol_ce == other.pol_ce);
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}
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};
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struct GClkNetInfo {
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// How many CE FFs on this CLK net have we seen?
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int net_size;
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// After ICG generation, we have new gated CLK signals
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Wire* new_net;
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};
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ClkNetInfo clk_info_from_ff(FfData& ff) {
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SigBit clk = ff.sig_clk[0];
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SigBit ce = ff.sig_ce[0];
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ClkNetInfo info{clk, ce, ff.pol_clk, ff.pol_ce};
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return info;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override {
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log_header(design, "Executing CLOCK_GATE pass (extract clock gating out of flip flops).\n");
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std::optional<ClockGateCell> pos_icg_desc;
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std::optional<ClockGateCell> neg_icg_desc;
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std::vector<std::string> tie_lo_ports;
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int min_net_size = 0;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-pos" && argidx+2 < args.size()) {
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auto name = args[++argidx];
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auto rest = args[++argidx];
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pos_icg_desc = icg_from_arg(name, rest);
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}
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if (args[argidx] == "-neg" && argidx+2 < args.size()) {
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auto name = args[++argidx];
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auto rest = args[++argidx];
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neg_icg_desc = icg_from_arg(name, rest);
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}
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if (args[argidx] == "-tie_lo" && argidx+1 < args.size()) {
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tie_lo_ports.push_back(RTLIL::escape_id(args[++argidx]));
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}
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if (args[argidx] == "-min_net_size" && argidx+1 < args.size()) {
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min_net_size = atoi(args[++argidx].c_str());
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}
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}
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extra_args(args, argidx, design);
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pool<Cell*> ce_ffs;
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dict<ClkNetInfo, GClkNetInfo> clk_nets;
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int gated_flop_count = 0;
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for (auto module : design->selected_whole_modules()) {
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for (auto cell : module->cells()) {
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if (!RTLIL::builtin_ff_cell_types().count(cell->type))
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continue;
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FfData ff(nullptr, cell);
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// It would be odd to get constants, but we better handle it
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if (ff.has_ce) {
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if (!ff.sig_clk.is_bit() || !ff.sig_ce.is_bit())
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continue;
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if (!ff.sig_clk[0].is_wire() || !ff.sig_ce[0].is_wire())
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continue;
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ce_ffs.insert(cell);
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ClkNetInfo info = clk_info_from_ff(ff);
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auto it = clk_nets.find(info);
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if (it == clk_nets.end())
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clk_nets[info] = GClkNetInfo();
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clk_nets[info].net_size++;
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}
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}
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for (auto& clk_net : clk_nets) {
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auto& clk = clk_net.first;
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auto& gclk = clk_net.second;
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if (gclk.net_size < min_net_size)
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continue;
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std::optional<ClockGateCell> matching_icg_desc;
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if (pos_icg_desc && clk.pol_clk)
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matching_icg_desc = pos_icg_desc;
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else if (neg_icg_desc && !clk.pol_clk)
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matching_icg_desc = neg_icg_desc;
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if (!matching_icg_desc)
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continue;
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Cell* icg = module->addCell(NEW_ID, matching_icg_desc->name);
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icg->setPort(matching_icg_desc->ce_pin, clk.ce_bit);
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icg->setPort(matching_icg_desc->clk_in_pin, clk.clk_bit);
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gclk.new_net = module->addWire(NEW_ID);
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icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net);
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// Tie low DFT ports like scan chain enable
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for (auto port : tie_lo_ports)
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icg->setPort(port, Const(0, 1));
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// Fix CE polarity if needed
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if (!clk.pol_ce) {
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SigBit ce_fixed_pol = module->NotGate(NEW_ID, clk.ce_bit);
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icg->setPort(matching_icg_desc->ce_pin, ce_fixed_pol);
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}
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}
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for (auto cell : ce_ffs) {
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FfData ff(nullptr, cell);
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ClkNetInfo info = clk_info_from_ff(ff);
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auto it = clk_nets.find(info);
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log_assert(it != clk_nets.end() && "Bug: desync ce_ffs and clk_nets");
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if (!it->second.new_net)
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continue;
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log_debug("Fix up FF %s\n", cell->name.c_str());
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// Now we start messing with the design
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ff.has_ce = false;
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// Construct the clock gate
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// ICG = integrated clock gate, industry shorthand
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ff.sig_clk = (*it).second.new_net;
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// Rebuild the flop
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(void)ff.emit();
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gated_flop_count++;
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}
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ce_ffs.clear();
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clk_nets.clear();
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}
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log("Converted %d FFs.\n", gated_flop_count);
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}
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} ClockgatePass;
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PRIVATE_NAMESPACE_END
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@ -0,0 +1,196 @@
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read_verilog << EOT
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module dffe_00( input clk, en,
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input d1, output reg q1,
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);
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always @( negedge clk ) begin
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if ( ~en )
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q1 <= d1;
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end
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endmodule
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module dffe_01( input clk, en,
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input d1, output reg q1,
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);
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always @( negedge clk ) begin
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if ( en )
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q1 <= d1;
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end
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endmodule
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module dffe_10( input clk, en,
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input d1, output reg q1,
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);
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always @( posedge clk ) begin
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if ( ~en )
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q1 <= d1;
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end
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endmodule
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module dffe_11( input clk, en,
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input d1, output reg q1,
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);
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always @( posedge clk ) begin
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if ( en )
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q1 <= d1;
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end
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endmodule
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module dffe_wide_11( input clk, en,
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input [3:0] d1, output reg [3:0] q1,
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);
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always @( posedge clk ) begin
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if ( en )
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q1 <= d1;
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end
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endmodule
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EOT
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proc
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opt
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design -save before
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#------------------------------------------------------------------------------
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# Test -pos
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clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
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# falling edge clock flops don't get matched on -pos
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select -module dffe_00 -assert-count 0 t:\\pdk_icg
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select -module dffe_01 -assert-count 0 t:\\pdk_icg
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# falling edge clock flops do get matched on -pos
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select -module dffe_10 -assert-count 1 t:\\pdk_icg
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select -module dffe_11 -assert-count 1 t:\\pdk_icg
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# if necessary, EN is inverted, since the given ICG
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# is assumed to have an active-high EN
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select -module dffe_10 -assert-count 1 t:\$_NOT_
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select -module dffe_11 -assert-count 0 t:\$_NOT_
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# Extra credit: multi-bit FFs work fine as well
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select -module dffe_wide_11 -assert-count 1 t:\\pdk_icg
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#------------------------------------------------------------------------------
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# Test -neg
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design -load before
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clockgate -min_net_size 1 -neg pdk_icg ce:clkin:clkout -tie_lo scanen
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# rising edge clock flops don't get matched on -neg
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select -module dffe_00 -assert-count 1 t:\\pdk_icg
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select -module dffe_01 -assert-count 1 t:\\pdk_icg
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# rising edge clock flops do get matched on -neg
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select -module dffe_10 -assert-count 0 t:\\pdk_icg
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select -module dffe_11 -assert-count 0 t:\\pdk_icg
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# if necessary, EN is inverted, since the given ICG
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# is assumed to have an active-high EN
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select -module dffe_00 -assert-count 1 t:\$_NOT_
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select -module dffe_01 -assert-count 0 t:\$_NOT_
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#------------------------------------------------------------------------------
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# Same as first case, but on fine-grained cells
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design -load before
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techmap
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clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
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# falling edge clock flops don't get matched on -pos
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select -module dffe_00 -assert-count 0 t:\\pdk_icg
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select -module dffe_01 -assert-count 0 t:\\pdk_icg
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# falling edge clock flops do get matched on -pos
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select -module dffe_10 -assert-count 1 t:\\pdk_icg
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select -module dffe_11 -assert-count 1 t:\\pdk_icg
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# if necessary, EN is inverted, since the given ICG
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# is assumed to have an active-high EN
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select -module dffe_10 -assert-count 1 t:\$_NOT_
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select -module dffe_11 -assert-count 0 t:\$_NOT_
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# Extra credit: multi-bit FFs work fine as well
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select -module dffe_wide_11 -assert-count 1 t:\\pdk_icg
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#------------------------------------------------------------------------------
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design -load before
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clockgate -min_net_size 2 -neg pdk_icg ce:clkin:clkout -tie_lo scanen
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# No FF set sharing a (clock, clock enable) pair is large enough
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select -module dffe_00 -assert-count 0 t:\\pdk_icg
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select -module dffe_01 -assert-count 0 t:\\pdk_icg
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select -module dffe_10 -assert-count 0 t:\\pdk_icg
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select -module dffe_11 -assert-count 0 t:\\pdk_icg
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#------------------------------------------------------------------------------
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design -reset
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read_rtlil << EOT
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module \bad1
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wire input 1 \clk
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wire input 3 \d1
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wire input 2 \en
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wire output 4 \q1
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cell $dffe $auto$ff.cc:266:slice$27
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parameter \CLK_POLARITY 1
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parameter \EN_POLARITY 1
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parameter \WIDTH 1
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connect \CLK \clk
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connect \D \d1
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connect \EN 1'1
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connect \Q \q1
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end
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end
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module \bad2
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wire input 1 \clk
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wire input 3 \d1
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wire input 2 \en
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wire output 4 \q1
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cell $dffe $auto$ff.cc:266:slice$27
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parameter \CLK_POLARITY 1
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parameter \EN_POLARITY 1
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parameter \WIDTH 1
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connect \CLK 1'1
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connect \D \d1
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connect \EN \en
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connect \Q \q1
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end
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end
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EOT
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# Check we don't choke on constants
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clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
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select -module bad1 -assert-count 0 t:\\pdk_icg
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select -module bad2 -assert-count 0 t:\\pdk_icg
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#------------------------------------------------------------------------------
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# Regression test: EN is a bit from a multi-bit wire
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design -reset
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read_verilog << EOT
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module dffe_wide_11( input clk, input [1:0] en,
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input [3:0] d1, output reg [3:0] q1,
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);
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always @( posedge clk ) begin
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if ( en[0] )
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q1 <= d1;
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end
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endmodule
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EOT
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proc
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opt
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clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
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select -assert-count 1 t:\\pdk_icg
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#------------------------------------------------------------------------------
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# TODO test -tie_lo
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