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xilinx: cleanup DSP48E1 handling for abc9

This commit is contained in:
Eddie Hung 2020-03-04 11:28:14 -08:00
parent f65fc845e5
commit 512596760b
3 changed files with 125 additions and 86 deletions
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45
techlibs/xilinx/abc9_map.v
View File

@ -771,38 +771,15 @@ module DSP48E1 (
.RSTM(RSTM), .RSTM(RSTM),
.RSTP(RSTP) .RSTP(RSTP)
); );
$__ABC9_DSP48E1 #(
generate .AREG(AREG),
wire [29:0] $A; .BREG(BREG),
wire [17:0] $B; .CREG(CREG),
wire [47:0] $C; .DREG(DREG),
wire [24:0] $D; .MREG(MREG),
wire [47:0] $PCIN; .PREG(PREG),
.USE_DPORT(USE_DPORT),
if (PREG == 0) begin .USE_MULT(USE_MULT)
if (MREG == 0 && AREG == 0) assign $A = A; ) dsp_comb (
else assign $A = 30'bx; .$A(A), .$B(B), .$C(C), .$D(D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
if (MREG == 0 && BREG == 0) assign $B = B;
else assign $B = 18'bx;
if (MREG == 0 && DREG == 0) assign $D = D;
else assign $D = 25'bx;
if (CREG == 0) assign $C = C;
else assign $C = 48'bx;
assign $PCIN = PCIN;
end
else begin
assign $A = 30'bx, $B = 18'bx, $C = 48'bx, $D = 25'bx, $PCIN = 48'bx;
end
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE")
$__ABC9_DSP48E1_MULT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN($PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE")
$__ABC9_DSP48E1_MULT_DPORT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN($PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE")
$__ABC9_DSP48E1 dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN($PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
else
$error("Invalid DSP48E1 configuration");
endgenerate
endmodule endmodule

138
techlibs/xilinx/abc9_model.v
View File

@ -94,10 +94,9 @@ module \$__ABC9_RAM7 (input A, input [6:0] S, output Y);
endspecify endspecify
endmodule endmodule
// Boxes used to represent the comb behaviour of various modes // Boxes used to represent the comb behaviour of DSP48E1
// of DSP48E1 (* abc9_box *)
`define ABC9_DSP48E1(__NAME__) """ module $__ABC9_DSP48E1 (
module __NAME__ (
input [29:0] $A, input [29:0] $A,
input [17:0] $B, input [17:0] $B,
input [47:0] $C, input [47:0] $C,
@ -106,50 +105,105 @@ module __NAME__ (
input [47:0] $PCIN, input [47:0] $PCIN,
input [47:0] $PCOUT, input [47:0] $PCOUT,
output [47:0] P, output [47:0] P,
output [47:0] PCOUT); output [47:0] PCOUT
""" );
(* abc9_box *) `ABC9_DSP48E1($__ABC9_DSP48E1_MULT) parameter integer AREG = 1;
parameter integer BREG = 1;
parameter integer CREG = 1;
parameter integer DREG = 1;
parameter integer MREG = 1;
parameter integer PREG = 1;
parameter USE_DPORT = "FALSE";
parameter USE_MULT = "MULTIPLY";
function integer \A.P.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.P.comb = 2823;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.P.comb = 3806;
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.P.comb = 1523;
end
endfunction
function integer \A.PCOUT.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \A.PCOUT.comb = 2970;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \A.PCOUT.comb = 3954;
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \A.PCOUT.comb = 1671;
end
endfunction
function integer \B.P.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.P.comb = 2690;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.P.comb = 2690;
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.P.comb = 1509;
end
endfunction
function integer \B.PCOUT.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \B.PCOUT.comb = 2838;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \B.PCOUT.comb = 2838;
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \B.PCOUT.comb = 1658;
end
endfunction
function integer \C.P.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.P.comb = 1325;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.P.comb = 1325;
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.P.comb = 1325;
end
endfunction
function integer \C.PCOUT.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \C.PCOUT.comb = 1474;
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE") \C.PCOUT.comb = 1474;
end
endfunction
function integer \D.P.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.P.comb = 3717;
end
endfunction
function integer \D.PCOUT.comb ;
begin
if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE") \D.PCOUT.comb = 3700;
end
endfunction
specify specify
($A *> P) = 2823;
($B *> P) = 2690;
($C *> P) = 1325;
($PCIN *> P) = 1107;
($P *> P) = 0; ($P *> P) = 0;
($A *> PCOUT) = 2970;
($B *> PCOUT) = 2838;
($C *> PCOUT) = 1474;
($PCIN *> PCOUT) = 1255;
($PCOUT *> PCOUT) = 0; ($PCOUT *> PCOUT) = 0;
endspecify endspecify
endmodule
(* abc9_box *) `ABC9_DSP48E1($__ABC9_DSP48E1_MULT_DPORT) // Identical comb delays to DSP48E1 in cells_sim.v
generate
if (PREG == 0 && MREG == 0 && AREG == 0)
specify specify
($A *> P) = 3806; ($A *> P) = \A.P.comb ();
($B *> P) = 2690; ($A *> PCOUT) = \A.PCOUT.comb ();
($C *> P) = 1325;
($D *> P) = 3717;
($PCIN *> P) = 1107;
($P *> P) = 0;
($A *> PCOUT) = 3954;
($B *> PCOUT) = 2838;
($C *> PCOUT) = 1474;
($D *> PCOUT) = 3700;
($PCIN *> PCOUT) = 1255;
($PCOUT *> PCOUT) = 0;
endspecify endspecify
endmodule
(* abc9_box *) `ABC9_DSP48E1($__ABC9_DSP48E1) if (PREG == 0 && MREG == 0 && BREG == 0)
specify specify
($A *> P) = 1523; ($B *> P) = \B.P.comb ();
($B *> P) = 1509; ($B *> PCOUT) = \B.PCOUT.comb ();
($C *> P) = 1325;
($PCIN *> P) = 1107;
($P *> P) = 0;
($A *> PCOUT) = 1671;
($B *> PCOUT) = 1658;
($C *> PCOUT) = 1474;
($PCIN *> PCOUT) = 1255;
($PCOUT *> PCOUT) = 0;
endspecify endspecify
if (PREG == 0 && CREG == 0)
specify
($C *> P) = \C.P.comb ();
($C *> PCOUT) = \C.PCOUT.comb ();
endspecify
if (PREG == 0 && MREG == 0 && DREG == 0)
specify
($D *> P) = \D.P.comb ();
($D *> PCOUT) = \D.PCOUT.comb ();
endspecify
if (PREG == 0)
specify
($PCIN *> P) = 1107;
($PCIN *> PCOUT) = 1255;
endspecify
endgenerate
endmodule endmodule
`undef ABC9_DSP48E1

12
techlibs/xilinx/abc9_unmap.v
View File

@ -36,8 +36,7 @@ module $__ABC9_RAM7(input A, input [6:0] S, output Y);
assign Y = A; assign Y = A;
endmodule endmodule
(* techmap_celltype = "$__ABC9_DSP48E1_MULT $__ABC9_DSP48E1_MULT_DPORT $__ABC9_DSP48E1" *) module $__ABC9_DSP48E1(
module $ABC9_DSP48E1(
input [29:0] $A, input [29:0] $A,
input [17:0] $B, input [17:0] $B,
input [47:0] $C, input [47:0] $C,
@ -48,5 +47,14 @@ module $ABC9_DSP48E1(
output [47:0] P, output [47:0] P,
output [47:0] PCOUT output [47:0] PCOUT
); );
parameter integer AREG = 1;
parameter integer BREG = 1;
parameter integer CREG = 1;
parameter integer DREG = 1;
parameter integer MREG = 1;
parameter integer PREG = 1;
parameter USE_DPORT = "FALSE";
parameter USE_MULT = "MULTIPLY";
assign P = $P, PCOUT = $PCOUT; assign P = $P, PCOUT = $PCOUT;
endmodule endmodule