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Drive $[ABCD] explicitly

This commit is contained in:
Eddie Hung 2020-01-02 13:28:37 -08:00
parent 3012e9eebc
commit 50b68777d3
1 changed files with 21 additions and 15 deletions
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36
techlibs/xilinx/abc9_map.v
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@ -373,22 +373,28 @@ module DSP48E1 (
wire [47:0] $C; wire [47:0] $C;
wire [24:0] $D; wire [24:0] $D;
if (PREG != 0) if (PREG == 0) begin
assign P = $P, PCOUT = $PCOUT; if (MREG == 0 && AREG == 0) assign $A = A;
else begin else assign $A = 30'bx;
if (AREG == 0) assign $A = A; if (MREG == 0 && BREG == 0) assign $B = B;
if (BREG == 0) assign $B = B; else assign $B = 18'bx;
if (CREG == 0) assign $C = C; if (MREG == 0 && DREG == 0) assign $D = D;
if (DREG == 0) assign $D = D; else assign $D = 25'bx;
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE") if (CREG == 0) assign $C = C;
$__ABC9_DSP48E1_MULT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT)); else assign $C = 48'bx;
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE")
$__ABC9_DSP48E1_MULT_DPORT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE")
$__ABC9_DSP48E1 dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
else
$error("Invalid DSP48E1 configuration");
end end
else begin
assign $A = 30'bx, $B = 18'bx, $C = 48'bx, $D = 25'bx;
end
if (USE_MULT == "MULTIPLY" && USE_DPORT == "FALSE")
$__ABC9_DSP48E1_MULT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
else if (USE_MULT == "MULTIPLY" && USE_DPORT == "TRUE")
$__ABC9_DSP48E1_MULT_DPORT dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
else if (USE_MULT == "NONE" && USE_DPORT == "FALSE")
$__ABC9_DSP48E1 dsp_comb(.$A($A), .$B($B), .$C($C), .$D($D), .$P($P), .$PCIN(PCIN), .$PCOUT($PCOUT), .P(P), .PCOUT(PCOUT));
else
$error("Invalid DSP48E1 configuration");
endgenerate endgenerate
endmodule endmodule