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Fixed "extract" pass for non-optimized needles

This commit is contained in:
Clifford Wolf 2013-02-27 23:19:30 +01:00
parent 1bbc2b34c8
commit 500786af55
1 changed files with 4 additions and 5 deletions
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9
passes/extract/extract.cc
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@ -158,18 +158,17 @@ namespace
RTLIL::Cell *needle_cell = (RTLIL::Cell*)mapping.needleUserData; RTLIL::Cell *needle_cell = (RTLIL::Cell*)mapping.needleUserData;
RTLIL::Cell *haystack_cell = (RTLIL::Cell*)mapping.haystackUserData; RTLIL::Cell *haystack_cell = (RTLIL::Cell*)mapping.haystackUserData;
for (auto &conn : needle_cell->connections) for (auto &conn : needle_cell->connections) {
if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(conn.second)) RTLIL::SigSpec sig = sigmap(conn.second);
{ if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) {
RTLIL::SigSpec sig = sigmap(conn.second);
sig.expand(); sig.expand();
for (int i = 0; i < sig.width; i++) for (int i = 0; i < sig.width; i++)
for (auto &port : sig2port.find(sig.chunks[i])) { for (auto &port : sig2port.find(sig.chunks[i])) {
RTLIL::SigSpec bitsig = haystack_cell->connections.at(mapping.portMapping[conn.first]).extract(i, 1); RTLIL::SigSpec bitsig = haystack_cell->connections.at(mapping.portMapping[conn.first]).extract(i, 1);
cell->connections.at(port.first).replace(port.second, bitsig); cell->connections.at(port.first).replace(port.second, bitsig);
} }
} }
}
haystack->cells.erase(haystack_cell->name); haystack->cells.erase(haystack_cell->name);
delete haystack_cell; delete haystack_cell;