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Merge pull request #1930 from YosysHQ/claire/fix1876 

Fix handling of ternary with constant condition
This commit is contained in:
Claire Wolf 2020-04-15 16:01:19 +02:00 committed by GitHub
parent 2e37e62e6b e7121cc15c
commit 4ee8fc1473
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 73 additions and 7 deletions
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20
frontends/ast/genrtlil.cc
View File

@ -1326,20 +1326,25 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
{ {
if (width_hint < 0) if (width_hint < 0)
detectSignWidth(width_hint, sign_hint); detectSignWidth(width_hint, sign_hint);
is_signed = sign_hint;
RTLIL::SigSpec cond = children[0]->genRTLIL(); RTLIL::SigSpec cond = children[0]->genRTLIL();
RTLIL::SigSpec sig; RTLIL::SigSpec sig;
if (cond.is_fully_const()) {
if (cond.is_fully_def())
{
if (cond.as_bool()) { if (cond.as_bool()) {
sig = children[1]->genRTLIL(width_hint, sign_hint); sig = children[1]->genRTLIL(width_hint, sign_hint);
widthExtend(this, sig, sig.size(), children[1]->is_signed); log_assert(is_signed == children[1]->is_signed);
} } else {
else {
sig = children[2]->genRTLIL(width_hint, sign_hint); sig = children[2]->genRTLIL(width_hint, sign_hint);
widthExtend(this, sig, sig.size(), children[2]->is_signed); log_assert(is_signed == children[2]->is_signed);
} }
widthExtend(this, sig, sig.size(), is_signed);
} }
else { else
{
RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint); RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint); RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
@ -1347,7 +1352,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
cond = uniop2rtlil(this, ID($reduce_bool), 1, cond, false); cond = uniop2rtlil(this, ID($reduce_bool), 1, cond, false);
int width = max(val1.size(), val2.size()); int width = max(val1.size(), val2.size());
is_signed = children[1]->is_signed && children[2]->is_signed; log_assert(is_signed == children[1]->is_signed);
log_assert(is_signed == children[2]->is_signed);
widthExtend(this, val1, width, is_signed); widthExtend(this, val1, width, is_signed);
widthExtend(this, val2, width, is_signed); widthExtend(this, val2, width, is_signed);

60
tests/various/bug1876.ys Normal file
View File

@ -0,0 +1,60 @@
read_verilog <<EOT
module expression_00032(b5, y15);
input signed [5:0] b5;
output [3:0] y15;
assign y15 = (0 ? b5 : b5) > 0;
endmodule
EOT
design -reset
read_verilog <<EOT
module expression_00057(a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y8);
input [3:0] a0;
input [4:0] a1;
input [5:0] a2;
input signed [3:0] a3;
input signed [4:0] a4;
input signed [5:0] a5;
input [3:0] b0;
input [4:0] b1;
input [5:0] b2;
input signed [3:0] b3;
input signed [4:0] b4;
input signed [5:0] b5;
output [5:0] y8;
localparam signed [4:0] p4 = ((2'd3)||(-4'sd1));
localparam signed [3:0] p9 = {3{(((2'sd0)^~(5'd20))>((-3'sd0)>>(4'sd2)))}};
assign y8 = (-(!($signed({3{p9}})<(p4?b4:b5))));
endmodule
EOT
design -reset
read_verilog <<EOT
module expression_00354(a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y4);
input [3:0] a0;
input [4:0] a1;
input [5:0] a2;
input signed [3:0] a3;
input signed [4:0] a4;
input signed [5:0] a5;
input [3:0] b0;
input [4:0] b1;
input [5:0] b2;
input signed [3:0] b3;
input signed [4:0] b4;
input signed [5:0] b5;
output wire signed [4:0] y4;
localparam signed [4:0] p10 = ((3'd0)?(2'd1):(-2'sd1));
assign y4 = ((p10?a4:b4)&$signed(b3));
endmodule
EOT