mirror of https://github.com/YosysHQ/yosys.git
simlib: blackbox `$print` cell
It's possible to `generate` the appropriate always blocks per the triggers, but unlikely to be worth parsing the RTLIL \FORMAT parameter.
This commit is contained in:
parent
fc0acd0ad1
commit
4e94f62116
|
@ -1799,6 +1799,23 @@ end
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
|
// --------------------------------------------------------
|
||||||
|
|
||||||
|
module \$print (EN, TRG, ARGS);
|
||||||
|
|
||||||
|
parameter FORMAT = "";
|
||||||
|
parameter ARGS_WIDTH = 0;
|
||||||
|
parameter TRG_ENABLE = 1;
|
||||||
|
|
||||||
|
parameter TRG_WIDTH = 0;
|
||||||
|
parameter TRG_POLARITY = 0;
|
||||||
|
|
||||||
|
input EN;
|
||||||
|
input [TRG_WIDTH-1:0] TRG;
|
||||||
|
input [ARGS_WIDTH-1:0] ARGS;
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
// --------------------------------------------------------
|
// --------------------------------------------------------
|
||||||
`ifndef SIMLIB_NOSR
|
`ifndef SIMLIB_NOSR
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue