From 4e94f62116cf4b9180a7a0ddb6ca4ad61a97bd53 Mon Sep 17 00:00:00 2001 From: Charlotte Date: Wed, 28 Jun 2023 11:51:27 +1000 Subject: [PATCH] simlib: blackbox `$print` cell It's possible to `generate` the appropriate always blocks per the triggers, but unlikely to be worth parsing the RTLIL \FORMAT parameter. --- techlibs/common/simlib.v | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 9cb68e725..32f2b6937 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1799,6 +1799,23 @@ end endmodule +// -------------------------------------------------------- + +module \$print (EN, TRG, ARGS); + +parameter FORMAT = ""; +parameter ARGS_WIDTH = 0; +parameter TRG_ENABLE = 1; + +parameter TRG_WIDTH = 0; +parameter TRG_POLARITY = 0; + +input EN; +input [TRG_WIDTH-1:0] TRG; +input [ARGS_WIDTH-1:0] ARGS; + +endmodule + // -------------------------------------------------------- `ifndef SIMLIB_NOSR