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xaiger: always sort input/output bits by port id 

redundant for normal design, but necessary for holes
This commit is contained in:
Eddie Hung 2020-04-15 16:16:30 -07:00
parent ec4bbb1444
commit 4c6647a469
1 changed files with 10 additions and 12 deletions
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6
backends/aiger/xaiger.cc
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@ -138,7 +138,7 @@ struct XAigerWriter
return a; return a;
} }
XAigerWriter(Module *module, bool dff_mode, bool holes_mode=false) : module(module), sigmap(module) XAigerWriter(Module *module, bool dff_mode) : module(module), sigmap(module)
{ {
pool<SigBit> undriven_bits; pool<SigBit> undriven_bits;
pool<SigBit> unused_bits; pool<SigBit> unused_bits;
@ -411,7 +411,6 @@ struct XAigerWriter
undriven_bits.erase(bit); undriven_bits.erase(bit);
} }
if (holes_mode) {
struct sort_by_port_id { struct sort_by_port_id {
bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const { bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
return a.wire->port_id < b.wire->port_id || return a.wire->port_id < b.wire->port_id ||
@ -420,7 +419,6 @@ struct XAigerWriter
}; };
input_bits.sort(sort_by_port_id()); input_bits.sort(sort_by_port_id());
output_bits.sort(sort_by_port_id()); output_bits.sort(sort_by_port_id());
}
aig_map[State::S0] = 0; aig_map[State::S0] = 0;
aig_map[State::S1] = 1; aig_map[State::S1] = 1;
@ -685,7 +683,7 @@ struct XAigerWriter
RTLIL::Module *holes_module = holes_design ? holes_design->module(module->name) : nullptr; RTLIL::Module *holes_module = holes_design ? holes_design->module(module->name) : nullptr;
if (holes_module) { if (holes_module) {
std::stringstream a_buffer; std::stringstream a_buffer;
XAigerWriter writer(holes_module, false /* dff_mode */, true /* holes_mode */); XAigerWriter writer(holes_module, false /* dff_mode */);
writer.write_aiger(a_buffer, false /*ascii_mode*/); writer.write_aiger(a_buffer, false /*ascii_mode*/);
f << "a"; f << "a";