riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #4177 from povik/connect-extra_args 

connect: Do interpret selection arguments
This commit is contained in:
N. Engelhardt 2024-02-19 15:18:37 +01:00 committed by GitHub
parent aebb7a0c4d a84fa0a277
commit 4b99db0b73
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
1 changed files with 15 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
passes/cmds/connect.cc
View File

@ -47,7 +47,7 @@ struct ConnectPass : public Pass {
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" connect [-nomap] [-nounset] -set <lhs-expr> <rhs-expr>\n");
log(" connect [-nomap] [-nounset] -set <lhs-expr> <rhs-expr> [selection]\n");
log("\n");
log("Create a connection. This is equivalent to adding the statement 'assign\n");
log("<lhs-expr> = <rhs-expr>;' to the Verilog input. Per default, all existing\n");
@ -55,12 +55,12 @@ struct ConnectPass : public Pass {
log("the -nounset option.\n");
log("\n");
log("\n");
log(" connect [-nomap] -unset <expr>\n");
log(" connect [-nomap] -unset <expr> [selection]\n");
log("\n");
log("Unconnect all existing drivers for the specified expression.\n");
log("\n");
log("\n");
log(" connect [-nomap] [-assert] -port <cell> <port> <expr>\n");
log(" connect [-nomap] [-assert] -port <cell> <port> <expr> [selection]\n");
log("\n");
log("Connect the specified cell port to the specified cell port.\n");
log("\n");
@ -80,17 +80,6 @@ struct ConnectPass : public Pass {
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
RTLIL::Module *module = nullptr;
for (auto mod : design->selected_modules()) {
if (module != nullptr)
log_cmd_error("Multiple modules selected: %s, %s\n", log_id(module->name), log_id(mod->name));
module = mod;
}
if (module == nullptr)
log_cmd_error("No modules selected.\n");
if (!module->processes.empty())
log_cmd_error("Found processes in selected module.\n");
bool flag_nounset = false, flag_nomap = false, flag_assert = false;
std::string set_lhs, set_rhs, unset_expr;
std::string port_cell, port_port, port_expr;
@ -128,6 +117,18 @@ struct ConnectPass : public Pass {
}
break;
}
extra_args(args, argidx, design);
RTLIL::Module *module = nullptr;
for (auto mod : design->selected_modules()) {
if (module != nullptr)
log_cmd_error("Multiple modules selected: %s, %s\n", log_id(module->name), log_id(mod->name));
module = mod;
}
if (module == nullptr)
log_cmd_error("No modules selected.\n");
if (!module->processes.empty())
log_cmd_error("Found processes in selected module.\n");
SigMap sigmap;
if (!flag_nomap)