mirror of https://github.com/YosysHQ/yosys.git
int -> bool
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@ -735,7 +735,7 @@ struct RTLIL::SigChunk
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RTLIL::SigChunk extract(int offset, int length) const;
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RTLIL::SigChunk extract(int offset, int length) const;
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inline int size() const { return width; }
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inline int size() const { return width; }
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inline int is_wire() const { return wire != NULL; }
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inline bool is_wire() const { return wire != NULL; }
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bool operator <(const RTLIL::SigChunk &other) const;
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bool operator <(const RTLIL::SigChunk &other) const;
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bool operator ==(const RTLIL::SigChunk &other) const;
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bool operator ==(const RTLIL::SigChunk &other) const;
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@ -761,7 +761,7 @@ struct RTLIL::SigBit
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SigBit(const RTLIL::SigBit &sigbit) = default;
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SigBit(const RTLIL::SigBit &sigbit) = default;
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RTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;
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RTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;
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inline int is_wire() const { return wire != NULL; }
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inline bool is_wire() const { return wire != NULL; }
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bool operator <(const RTLIL::SigBit &other) const;
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bool operator <(const RTLIL::SigBit &other) const;
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bool operator ==(const RTLIL::SigBit &other) const;
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bool operator ==(const RTLIL::SigBit &other) const;
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