mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #676 from rafaeltp/master
Splits SigSpec into bits before calling check_signal_in_fanout (solves #675)
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commit
47c89d600c
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@ -290,22 +290,29 @@ struct EquivMakeWorker
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init_bit2driven();
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init_bit2driven();
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pool<Cell*> visited_cells;
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pool<Cell*> visited_cells;
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for (auto c : cells_list)
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for (auto c : cells_list)
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for (auto &conn : c->connections())
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for (auto &conn : c->connections())
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if (!ct.cell_output(c->type, conn.first)) {
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if (!ct.cell_output(c->type, conn.first)) {
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SigSpec old_sig = assign_map(conn.second);
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SigSpec old_sig = assign_map(conn.second);
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SigSpec new_sig = rd_signal_map(old_sig);
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SigSpec new_sig = rd_signal_map(old_sig);
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visited_cells.clear();
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if (old_sig != new_sig) {
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if (check_signal_in_fanout(visited_cells, old_sig, new_sig))
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continue;
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log("Changing input %s of cell %s (%s): %s -> %s\n",
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if(old_sig != new_sig) {
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log_id(conn.first), log_id(c), log_id(c->type),
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SigSpec tmp_sig = old_sig;
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log_signal(old_sig), log_signal(new_sig));
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for (int i = 0; i < GetSize(old_sig); i++) {
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c->setPort(conn.first, new_sig);
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SigBit old_bit = old_sig[i], new_bit = new_sig[i];
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visited_cells.clear();
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if (check_signal_in_fanout(visited_cells, old_bit, new_bit))
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continue;
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log("Changing input %s of cell %s (%s): %s -> %s\n",
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log_id(conn.first), log_id(c), log_id(c->type),
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log_signal(old_bit), log_signal(new_bit));
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tmp_sig[i] = new_bit;
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}
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c->setPort(conn.first, tmp_sig);
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}
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}
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}
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}
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