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Tested and working altsyncarm without init files

This commit is contained in:
dh73 2017-10-01 19:59:45 -05:00
parent e480847753
commit 4718e65763
2 changed files with 59 additions and 57 deletions
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70
techlibs/intel/common/brams_map.v
View File

@ -31,44 +31,42 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A
CFG_DBITS == 36 ? 9: CFG_DBITS == 36 ? 9:
'bx; 'bx;
localparam NUMWORDS = CFG_DBITS == 1 ? "8192": localparam NUMWORDS = CFG_DBITS == 1 ? 8192:
CFG_DBITS == 2 ? "4096": CFG_DBITS == 2 ? 4096:
CFG_DBITS == 4 ? "2048": CFG_DBITS == 4 ? 2048:
CFG_DBITS == 8 ? "1024": CFG_DBITS == 8 ? 1024:
CFG_DBITS == 9 ? "1024": CFG_DBITS == 9 ? 1024:
CFG_DBITS == 16 ? "512": CFG_DBITS == 16 ? 512:
CFG_DBITS == 18 ? "512": CFG_DBITS == 18 ? 512:
CFG_DBITS == 32 ? "256": CFG_DBITS == 32 ? 256:
CFG_DBITS == 36 ? "256": CFG_DBITS == 36 ? 256:
'bx; 'bx;
/* Killing some stupid warnings and assignations*/
/* generate
if( MODE == 1 ) begin
assign B1DATA_t = ({34{1'b0},B1DATA[0]});
end
endgenerate*/
altsyncram #(.clock_enable_input_b ("ALTERNATE" ), altsyncram #(.clock_enable_input_b ("ALTERNATE" ),
.clock_enable_input_a ("ALTERNATE" ), .clock_enable_input_a ("ALTERNATE" ),
.clock_enable_output_b ("NORMAL" ), .clock_enable_output_b ("NORMAL" ),
.clock_enable_output_a ("NORMAL" ), .clock_enable_output_a ("NORMAL" ),
.wrcontrol_aclr_a ("NONE" ), .wrcontrol_aclr_a ("NONE" ),
.indata_aclr_a ("NONE" ), .indata_aclr_a ("NONE" ),
.address_aclr_a ("NONE" ), .address_aclr_a ("NONE" ),
.outdata_aclr_a ("NONE" ), .outdata_aclr_a ("NONE" ),
.outdata_reg_a ("UNREGISTERED"), .outdata_reg_a ("UNREGISTERED"),
.operation_mode ("SINGLE_PORT" ), .operation_mode ("SINGLE_PORT" ),
.intended_device_family ("CYCLONE IVE" ), .intended_device_family ("CYCLONE IVE" ),
.outdata_reg_a ("UNREGISTERED"), .outdata_reg_a ("UNREGISTERED"),
.lpm_type ("altsyncram" ), .lpm_type ("altsyncram" ),
.init_type ("unused" ), .init_type ("unused" ),
.ram_block_type ("AUTO" ), .ram_block_type ("AUTO" ),
.numwords_b ( NUMWORDS ), .lpm_hint ("ENABLE_RUNTIME_MOD=NO"), // Forced value
.numwords_a ( NUMWORDS ), .power_up_uninitialized ("FALSE"),
.widthad_b ( CFG_ABITS ), .read_during_write_mode_port_a ("NEW_DATA_NO_NBE_READ"), // Forced value
.width_b ( CFG_DBITS ), .width_byteena_a (1), // Forced value
.widthad_a ( CFG_ABITS ), .numwords_b ( NUMWORDS ),
.width_a ( CFG_DBITS ) .numwords_a ( NUMWORDS ),
.widthad_b ( CFG_ABITS ),
.width_b ( CFG_DBITS ),
.widthad_a ( CFG_ABITS ),
.width_a ( CFG_DBITS )
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
.data_a(B1DATA), .data_a(B1DATA),
.address_a(B1ADDR), .address_a(B1ADDR),

46
techlibs/intel/common/m9k_bb.v
View File

@ -21,27 +21,31 @@ module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wr
q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1, q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1,
addressstall_a, addressstall_b); addressstall_a, addressstall_b);
parameter clock_enable_input_b = "ALTERNATE"; parameter clock_enable_input_b = "ALTERNATE";
parameter clock_enable_input_a = "ALTERNATE"; parameter clock_enable_input_a = "ALTERNATE";
parameter clock_enable_output_b = "NORMAL"; parameter clock_enable_output_b = "NORMAL";
parameter clock_enable_output_a = "NORMAL"; parameter clock_enable_output_a = "NORMAL";
parameter wrcontrol_aclr_a = "NONE"; parameter wrcontrol_aclr_a = "NONE";
parameter indata_aclr_a = "NONE"; parameter indata_aclr_a = "NONE";
parameter address_aclr_a = "NONE"; parameter address_aclr_a = "NONE";
parameter outdata_aclr_a = "NONE"; parameter outdata_aclr_a = "NONE";
parameter outdata_reg_a = "UNREGISTERED"; parameter outdata_reg_a = "UNREGISTERED";
parameter operation_mode = "SINGLE_PORT"; parameter operation_mode = "SINGLE_PORT";
parameter intended_device_family = "MAX 10 FPGA"; parameter intended_device_family = "MAX 10 FPGA";
parameter outdata_reg_a = "UNREGISTERED"; parameter outdata_reg_a = "UNREGISTERED";
parameter lpm_type = "altsyncram"; parameter lpm_type = "altsyncram";
parameter init_type = "unused"; parameter init_type = "unused";
parameter ram_block_type = "AUTO"; parameter ram_block_type = "AUTO";
parameter numwords_b = 0; parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO";
parameter numwords_a = 0; parameter power_up_uninitialized = "FALSE";
parameter widthad_b = 1; parameter read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ";
parameter width_b = 1; parameter width_byteena_a = 1;
parameter widthad_a = 1; parameter numwords_b = 0;
parameter width_a = 1; parameter numwords_a = 0;
parameter widthad_b = 1;
parameter width_b = 1;
parameter widthad_a = 1;
parameter width_a = 1;
// Port A declarations // Port A declarations
output [35:0] q_a; output [35:0] q_a;