ecp5: deprecate abc9_{arrival,required} and *.{lut,box}

techlibs/ecp5/Makefile.inc

@@ -18,9 +18,6 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/dsp_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_map.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_unmap.v))
 $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_model.v))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.box))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g.lut))
-$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc9_5g_nowide.lut))
 
 EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
 .SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk

techlibs/ecp5/abc9_5g.box

@@ -1,36 +0,0 @@
-# NB: Box inputs/outputs must each be in the same order
-#     as their corresponding module definition
-#     (with exceptions detailed below)
-
-# Box 1 : CCU2C (2xCARRY + 2xLUT4)
-#   (Exception: carry chain input/output must be the
-#        last input and output and the entire bus has been
-#        moved there overriding the otherwise
-#        alphabetical ordering)
-# name  ID   w/b   ins    outs
-CCU2C   1      1   9      3
-#A0  B0   C0    D0   A1   B1   C1   D1   CIN
-379  379  275   141  -    -    -    -    257 # S0
-630  630  526   392  379  379  275  141  273 # S1
-516  516  412   278  516  516  412  278   43 # COUT
-
-# Box 2 : TRELLIS_DPR16X4_COMB (16x4 dist ram)
-# name               ID  w/b   ins   outs
-$__ABC9_DPR16X4_COMB  2     0   8    4
-#$DO0 $DO1 $DO2 $DO3 RAD0   RAD1   RAD2   RAD3
-0     0    0    0    141    379    275    379 # DO0
-0     0    0    0    141    379    275    379 # DO1
-0     0    0    0    141    379    275    379 # DO2
-0     0    0    0    141    379    275    379 # DO3
-
-# Box 3 : PFUMX (MUX2)
-# name  ID   w/b   ins    outs
-PFUMX   3    1     3      1
-#ALUT  BLUT  C0
-98     98    151 # Z
-
-# Box 4 : L6MUX21 (MUX2)
-# name   ID   w/b   ins    outs
-L6MUX21  4    1     3      1
-#D0    D1    SD
-140    141   148 # Z

techlibs/ecp5/abc9_5g.lut

@@ -1,25 +0,0 @@
-# ECP5-5G LUT library for ABC
-# Note that ECP5 architecture assigns difference
-# in LUT input delay to interconnect, so this is
-# considered too
-
-
-# Simple LUTs
-#  area  D    C    B    A
-1  1     141
-2  1     141  275
-3  1     141  275  379
-4  1     141  275  379  379
-
-# LUT5 = 2x LUT4 + PFUMX
-#  area  M0   D    C    B    A
-5  2     151  239  373  477  477
-
-# LUT6 = 2x LUT5 + MUX2
-#  area  M1   M0   D    C    B    A
-6  4     148  292  380  514  618  618
-
-# LUT7 = 2x LUT6 + MUX2
-#  area  M2   M1   M0   D    C    B    A
-7  8     148  289  433  521  655  759  759
-

techlibs/ecp5/abc9_5g_nowide.lut

@@ -1,12 +0,0 @@
-# ECP5-5G LUT library for ABC
-# Note that ECP5 architecture assigns difference
-# in LUT input delay to interconnect, so this is
-# considered too
-
-
-# Simple LUTs
-#  area  D    C    B    A
-1  1     141
-2  1     141  275
-3  1     141  275  379
-4  1     141  275  379  379

techlibs/ecp5/abc9_model.v

@@ -1,5 +1,12 @@
 // ---------------------------------------
 
-(* abc9_box_id=2 *)
+(* abc9_box *)
 module \$__ABC9_DPR16X4_COMB (input [3:0] $DO, RAD, output [3:0] DO);
+  specify
+    ($DO => DO) = 0;
+    (RAD[0] *> DO) = 141;
+    (RAD[1] *> DO) = 379;
+    (RAD[2] *> DO) = 275;
+    (RAD[3] *> DO) = 379;
+  endspecify
 endmodule

techlibs/ecp5/cells_sim.v

@@ -1,22 +1,96 @@
 // ---------------------------------------
 
-(* lib_whitebox *)
+(* abc9_lut=1, lib_whitebox *)
 module LUT4(input A, B, C, D, output Z);
     parameter [15:0] INIT = 16'h0000;
     wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];
     wire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];
     wire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];
     assign Z =      A ?          s1[1] :         s1[0];
+    specify
+        (A => Z) = 141;
+        (B => Z) = 275;
+        (C => Z) = 379;
+        (D => Z) = 379;
+    endspecify
+endmodule
+
+(* abc9_lut=1 *)
+module \$__ABC9_LUT1 (input A, output Z);
+    specify
+        (A => Z) = 141;
+    endspecify
+endmodule
+
+(* abc9_lut=1 *)
+module \$__ABC9_LUT2 (input A, B, output Z);
+    specify
+        (A => Z) = 141;
+        (B => Z) = 275;
+    endspecify
+endmodule
+
+(* abc9_lut=1 *)
+module \$__ABC9_LUT3 (input A, B, C, output Z);
+    specify
+        (A => Z) = 141;
+        (B => Z) = 275;
+        (C => Z) = 379;
+    endspecify
+endmodule
+
+// LUT5 = 2x LUT4 + PFUMX
+(* abc9_lut=2 *)
+module \$__ABC9_LUT5 (input M0, D, C, B, A, output Z);
+    specify
+        (M0 => Z) = 151;
+        (D => Z) = 239;
+        (C => Z) = 373;
+        (B => Z) = 477;
+        (A => Z) = 477;
+    endspecify
+endmodule
+
+// LUT6 = 2x LUT5 + MUX2
+(* abc9_lut=4 *)
+module \$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);
+    specify
+        (M1 => Z) = 148;
+        (M0 => Z) = 292;
+        (D => Z) = 380;
+        (C => Z) = 514;
+        (B => Z) = 618;
+        (A => Z) = 618;
+    endspecify
+endmodule
+
+// LUT7 = 2x LUT6 + MUX2
+(* abc9_lut=8 *)
+module \$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z);
+    specify
+        (M2 => Z) = 148;
+        (M1 => Z) = 289;
+        (M0 => Z) = 433;
+        (D => Z) = 521;
+        (C => Z) = 655;
+        (B => Z) = 759;
+        (A => Z) = 759;
+    endspecify
 endmodule
 
 // ---------------------------------------
-(* abc9_box_id=4, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
 module L6MUX21 (input D0, D1, SD, output Z);
 	assign Z = SD ? D1 : D0;
+	specify
+		(D0 => Z) = 140;
+		(D1 => Z) = 141;
+		(SD => Z) = 148;
+	endspecify
 endmodule
 
 // ---------------------------------------
-(* abc9_box_id=1, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
 module CCU2C(
 	(* abc9_carry *)
 	input  CIN,
@@ -50,6 +124,31 @@ module CCU2C(
 	wire gated_lut2_1 = (INJECT1_1 == "YES") ? 1'b0 : LUT2_1;
 	assign COUT = (~LUT4_1 & gated_lut2_1) | (LUT4_1 & cout_0);
 
+	specify
+		(A0 => S0) = 379;
+		(B0 => S0) = 379;
+		(C0 => S0) = 275;
+		(D0 => S0) = 141;
+		(CIN => S0) = 257;
+		(A0 => S1) = 630;
+		(B0 => S1) = 630;
+		(C0 => S1) = 526;
+		(D0 => S1) = 392;
+		(A1 => S1) = 379;
+		(B1 => S1) = 379;
+		(C1 => S1) = 275;
+		(D1 => S1) = 141;
+		(CIN => S1) = 273;
+		(A0 => COUT) = 516;
+		(B0 => COUT) = 516;
+		(C0 => COUT) = 412;
+		(D0 => COUT) = 278;
+		(A1 => COUT) = 516;
+		(B1 => COUT) = 516;
+		(C1 => COUT) = 412;
+		(D1 => COUT) = 278;
+		(CIN => COUT) = 43;
+	endspecify
 endmodule
 
 // ---------------------------------------
@@ -94,9 +193,14 @@ module TRELLIS_RAM16X2 (
 endmodule
 
 // ---------------------------------------
-(* abc9_box_id=3, lib_whitebox *)
+(* abc9_box, lib_whitebox *)
 module PFUMX (input ALUT, BLUT, C0, output Z);
 	assign Z = C0 ? ALUT : BLUT;
+	specify
+		(ALUT => Z) = 98;
+		(BLUT => Z) = 98;
+		(C0 => Z) = 151;
+	endspecify
 endmodule
 
 // ---------------------------------------
@@ -106,7 +210,6 @@ module TRELLIS_DPR16X4 (
 	input        WRE,
 	input        WCK,
 	input  [3:0] RAD,
-	/* (* abc9_arrival=<TODO> *) */
 	output [3:0] DO
 );
 	parameter WCKMUX = "WCK";

techlibs/ecp5/synth_ecp5.cc

@@ -230,7 +230,7 @@ struct SynthEcp5Pass : public ScriptPass
 	{
 		if (check_label("begin"))
 		{
-			run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
+			run("read_verilog -lib -specify +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
 			run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
 		}
 
@@ -322,11 +322,11 @@ struct SynthEcp5Pass : public ScriptPass
 				run("techmap " + techmap_args);
 
 			if (abc9) {
-				run("read_verilog -icells -lib +/ecp5/abc9_model.v");
+				run("read_verilog -icells -lib -specify +/ecp5/abc9_model.v");
 				if (nowidelut)
-					run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200");
+					run("abc9 -maxlut 4 -W 200");
 				else
-					run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200");
+					run("abc9 -W 200");
 				run("techmap -map +/ecp5/abc9_unmap.v");
 			} else {
 				if (nowidelut)