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abc9_ops: -reintegrate to not trim box padding anymore

This commit is contained in:
Eddie Hung 2020-01-14 14:27:29 -08:00
parent 654247abe9
commit 4656f202c6
2 changed files with 1 additions and 10 deletions
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2
backends/aiger/xaiger.cc
View File

@ -349,7 +349,7 @@ struct XAigerWriter
unused_bits.erase(I); unused_bits.erase(I);
} }
if (w->port_output) if (w->port_output)
for (const auto &b : rhs.bits()) { for (const auto &b : rhs) {
SigBit O = sigmap(b); SigBit O = sigmap(b);
if (O != b) if (O != b)
alias_map[O] = b; alias_map[O] = b;

9
passes/techmap/abc9_ops.cc
View File

@ -562,15 +562,6 @@ void reintegrate(RTLIL::Module *module)
c.wire = module->wires_.at(remap_name(c.wire->name)); c.wire = module->wires_.at(remap_name(c.wire->name));
newsig.append(c); newsig.append(c);
} }
auto it = existing_cell->connections_.find(port_name);
if (it == existing_cell->connections_.end())
continue;
if (GetSize(newsig) > GetSize(it->second))
newsig = newsig.extract(0, GetSize(it->second));
else
log_assert(GetSize(newsig) == GetSize(it->second));
cell->setPort(port_name, newsig); cell->setPort(port_name, newsig);
if (w->port_input && !abc9_flop) if (w->port_input && !abc9_flop)