From 4656f202c6f05d126c1acc79fca675e467c80840 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 14 Jan 2020 14:27:29 -0800
Subject: [PATCH] abc9_ops: -reintegrate to not trim box padding anymore

---
 backends/aiger/xaiger.cc   | 2 +-
 passes/techmap/abc9_ops.cc | 9 ---------
 2 files changed, 1 insertion(+), 10 deletions(-)

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index f9890a592..4f466d568 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -349,7 +349,7 @@ struct XAigerWriter
 						unused_bits.erase(I);
 					}
 				if (w->port_output)
-					for (const auto &b : rhs.bits()) {
+					for (const auto &b : rhs) {
 						SigBit O = sigmap(b);
 						if (O != b)
 							alias_map[O] = b;
diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 463941b0b..aa21ff283 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -562,15 +562,6 @@ void reintegrate(RTLIL::Module *module)
 						c.wire = module->wires_.at(remap_name(c.wire->name));
 					newsig.append(c);
 				}
-
-				auto it = existing_cell->connections_.find(port_name);
-				if (it == existing_cell->connections_.end())
-					continue;
-				if (GetSize(newsig) > GetSize(it->second))
-					newsig = newsig.extract(0, GetSize(it->second));
-				else
-					log_assert(GetSize(newsig) == GetSize(it->second));
-
 				cell->setPort(port_name, newsig);
 
 				if (w->port_input && !abc9_flop)