riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

A or B width extend

This commit is contained in:
Alain Dargelas 2024-12-18 21:48:33 -08:00
parent 7270cd3979
commit 45500f4dd9
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
passes/pmgen/peepopt_muxadd.pmg
View File

@ -24,8 +24,8 @@ endmatch
code add_y add_a add_b add_a_ext
// Get adder signals
add_a_ext = SigSpec(add_a);
add_a_ext.extend_u0(GetSize(add_y), param(add, \A_SIGNED).as_bool());
add_a_ext = SigSpec(port(add, add_a_id));
add_a_ext.extend_u0(GetSize(add_y), add_a_signed.as_bool());
// Fanout of each adder Y bit should be 1 (no bit-split)
if (nusers(add_y) != 2)
reject;