mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #10 from alainmarcel/new_peepopts
Remove redundant code
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commit
7270cd3979
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@ -24,9 +24,6 @@ endmatch
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code add_y add_a add_b add_a_ext
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// Get adder signals
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add_a = port(add, \A);
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add_b = port(add, \B);
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add_y = port(add, \Y);
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add_a_ext = SigSpec(add_a);
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add_a_ext.extend_u0(GetSize(add_y), param(add, \A_SIGNED).as_bool());
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// Fanout of each adder Y bit should be 1 (no bit-split)
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