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use "hierarchy -auto-top" in synth_ice40

This commit is contained in:
Clifford Wolf 2015-04-14 13:45:15 +02:00
parent 06ce496f8d
commit 4529c56cc6
1 changed files with 3 additions and 3 deletions
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6
techlibs/ice40/synth_ice40.cc
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@ -85,14 +85,14 @@ struct SynthIce40Pass : public Pass {
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{ {
std::string top_module = "top"; std::string top_opt = "-auto-top";
std::string run_from, run_to; std::string run_from, run_to;
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++)
{ {
if (args[argidx] == "-top" && argidx+1 < args.size()) { if (args[argidx] == "-top" && argidx+1 < args.size()) {
top_module = args[++argidx]; top_opt = "-top " + args[++argidx];
continue; continue;
} }
if (args[argidx] == "-run" && argidx+1 < args.size()) { if (args[argidx] == "-run" && argidx+1 < args.size()) {
@ -118,7 +118,7 @@ struct SynthIce40Pass : public Pass {
if (check_label(active, run_from, run_to, "begin")) if (check_label(active, run_from, run_to, "begin"))
{ {
Pass::call(design, "read_verilog -lib +/ice40/cells_sim.v"); Pass::call(design, "read_verilog -lib +/ice40/cells_sim.v");
Pass::call(design, stringf("hierarchy -check -top %s", top_module.c_str())); Pass::call(design, stringf("hierarchy -check %s", top_opt.c_str()));
} }
if (check_label(active, run_from, run_to, "coarse")) if (check_label(active, run_from, run_to, "coarse"))