Merge pull request #3838 from povik/various-cleanup

README.md

@@ -156,9 +156,10 @@ reading and elaborating the design using the Verilog frontend:
 	yosys> read -sv tests/simple/fiedler-cooley.v
 	yosys> hierarchy -top up3down5
 
-writing the design to the console in Yosys's internal format:
+writing the design to the console in the RTLIL format used by Yosys
+internally:
 
-	yosys> write_ilang
+	yosys> write_rtlil
 
 convert processes (``always`` blocks) to netlist elements and perform
 some simple optimizations:

backends/blif/blif.cc

@@ -512,8 +512,8 @@ struct BlifBackend : public Backend {
 		log("        suppresses the generation of this nets without fanout.\n");
 		log("\n");
 		log("The following options can be useful when the generated file is not going to be\n");
-		log("read by a BLIF parser but a custom tool. It is recommended to not name the\n");
+		log("read by a BLIF parser but a custom tool. It is recommended not to name the\n");
-		log("output file *.blif when any of this options is used.\n");
+		log("output file *.blif when any of these options are used.\n");
 		log("\n");
 		log("    -icells\n");
 		log("        do not translate Yosys's internal gates to generic BLIF logic\n");

backends/firrtl/firrtl.cc

@@ -21,7 +21,6 @@
 #include "kernel/register.h"
 #include "kernel/sigtools.h"
 #include "kernel/celltypes.h"
-#include "kernel/cellaigs.h"
 #include "kernel/log.h"
 #include "kernel/mem.h"
 #include <algorithm>
@@ -1196,6 +1195,7 @@ struct FirrtlBackend : public Backend {
 		log("        pmuxtree\n");
 		log("        bmuxmap\n");
 		log("        demuxmap\n");
+		log("        bwmuxmap\n");
 		log("\n");
 	}
 	void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override

backends/jny/jny.cc

@@ -21,7 +21,6 @@
 #include "kernel/register.h"
 #include "kernel/sigtools.h"
 #include "kernel/celltypes.h"
-#include "kernel/cellaigs.h"
 #include "kernel/log.h"
 #include <string>
 #include <algorithm>

kernel/cellaigs.cc

@@ -318,7 +318,7 @@ Aig::Aig(Cell *cell)
 		goto optimize;
 	}
 
-	if (cell->type.in(ID($mux), ID($_MUX_)))
+	if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_)))
 	{
 		int S = mk.inport(ID::S);
 		for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) {

passes/techmap/extract_counter.cc

@@ -120,8 +120,6 @@ struct CounterExtractionSettings
 };
 
 //attempt to extract a counter centered on the given adder cell
-//For now we only support DOWN counters.
-//TODO: up/down support
 int counter_tryextract(
 	ModIndex& index,
 	Cell *cell,
@@ -766,9 +764,9 @@ struct ExtractCounterPass : public Pass {
 		log("\n");
 		log("    extract_counter [options] [selection]\n");
 		log("\n");
-		log("This pass converts non-resettable or async resettable down counters to\n");
+		log("This pass converts non-resettable or async resettable counters to counter cells.\n");
-		log("counter cells. Use a target-specific 'techmap' map file to convert those cells\n");
+		log("Use a target-specific 'techmap' map file to convert those cells to the actual\n");
-		log("to the actual target cells.\n");
+		log("target cells.\n");
 		log("\n");
 		log("    -maxwidth N\n");
 		log("        Only extract counters up to N bits wide (default 64)\n");

tests/various/help.ys

@@ -1,2 +1,2 @@
 help -all
-help -celltypes
+help -cells