From 06256c0c000e393a90f8447b32695d2296de09aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 10 Jul 2023 12:20:19 +0200 Subject: [PATCH 1/7] Slightly adjust the wording of "write_blif" help --- backends/blif/blif.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc index 23d1d58fc..8e2c088c4 100644 --- a/backends/blif/blif.cc +++ b/backends/blif/blif.cc @@ -512,8 +512,8 @@ struct BlifBackend : public Backend { log(" suppresses the generation of this nets without fanout.\n"); log("\n"); log("The following options can be useful when the generated file is not going to be\n"); - log("read by a BLIF parser but a custom tool. It is recommended to not name the\n"); - log("output file *.blif when any of this options is used.\n"); + log("read by a BLIF parser but a custom tool. It is recommended not to name the\n"); + log("output file *.blif when any of these options are used.\n"); log("\n"); log(" -icells\n"); log(" do not translate Yosys's internal gates to generic BLIF logic\n"); From 7c6cc4c40ba1ab59652da1201271ca8936523274 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 10 Jul 2023 12:20:48 +0200 Subject: [PATCH 2/7] tests: Fix invocation of 'help -cells' There's no such thing as 'help -celltypes' and there probably never was. --- tests/various/help.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/various/help.ys b/tests/various/help.ys index 9283ce8f1..04793274b 100644 --- a/tests/various/help.ys +++ b/tests/various/help.ys @@ -1,2 +1,2 @@ help -all -help -celltypes +help -cells From c0b1a7daa4f6f0f3430367096fb2cf41f7e3dbc8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 10 Jul 2023 12:21:49 +0200 Subject: [PATCH 3/7] Drop stray 'cellaigs.h' include from backend passes This include seems to have been copied over from the JSON backend where AIG models are sometimes inserted into the JSON output, but these other backends don't do anything with AIG. --- backends/firrtl/firrtl.cc | 1 - backends/jny/jny.cc | 1 - 2 files changed, 2 deletions(-) diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index eb30ab4b9..531b2f01f 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -21,7 +21,6 @@ #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/celltypes.h" -#include "kernel/cellaigs.h" #include "kernel/log.h" #include "kernel/mem.h" #include diff --git a/backends/jny/jny.cc b/backends/jny/jny.cc index 0be11a52c..9989feed5 100644 --- a/backends/jny/jny.cc +++ b/backends/jny/jny.cc @@ -21,7 +21,6 @@ #include "kernel/register.h" #include "kernel/sigtools.h" #include "kernel/celltypes.h" -#include "kernel/cellaigs.h" #include "kernel/log.h" #include #include From 78d13d195693df897b9d427c91e17b9f0dc6f2be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 10 Jul 2023 12:22:58 +0200 Subject: [PATCH 4/7] Mention 'bwmuxmap' in 'write_firrtl' help The FIRRTL backend does call into the 'bwmuxmap' pass but omits it in the help message. --- backends/firrtl/firrtl.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc index 531b2f01f..fc1d62891 100644 --- a/backends/firrtl/firrtl.cc +++ b/backends/firrtl/firrtl.cc @@ -1195,6 +1195,7 @@ struct FirrtlBackend : public Backend { log(" pmuxtree\n"); log(" bmuxmap\n"); log(" demuxmap\n"); + log(" bwmuxmap\n"); log("\n"); } void execute(std::ostream *&f, std::string filename, std::vector args, RTLIL::Design *design) override From 8839d7fa5a60214e1ff54fc2fdec8a33b27731cc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 10 Jul 2023 12:27:50 +0200 Subject: [PATCH 5/7] cellaigs: Fix the case of $_NMUX_ cells Later on there's a if (cell->type == ID($_NMUX_)) but that code was unreachable until now. --- kernel/cellaigs.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc index 292af3f51..c0d413fad 100644 --- a/kernel/cellaigs.cc +++ b/kernel/cellaigs.cc @@ -318,7 +318,7 @@ Aig::Aig(Cell *cell) goto optimize; } - if (cell->type.in(ID($mux), ID($_MUX_))) + if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_))) { int S = mk.inport(ID::S); for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) { From eb083c5d4b464378180d6e4ba2a890eeba656c1c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 10 Jul 2023 12:34:04 +0200 Subject: [PATCH 6/7] extract_counter: Update help and comments after UP/DOWN support Commit fec7dc5c should have added support for up counters so update the help and comments accordingly. --- passes/techmap/extract_counter.cc | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index 9c814af23..b780f7df0 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -120,8 +120,6 @@ struct CounterExtractionSettings }; //attempt to extract a counter centered on the given adder cell -//For now we only support DOWN counters. -//TODO: up/down support int counter_tryextract( ModIndex& index, Cell *cell, @@ -766,9 +764,9 @@ struct ExtractCounterPass : public Pass { log("\n"); log(" extract_counter [options] [selection]\n"); log("\n"); - log("This pass converts non-resettable or async resettable down counters to\n"); - log("counter cells. Use a target-specific 'techmap' map file to convert those cells\n"); - log("to the actual target cells.\n"); + log("This pass converts non-resettable or async resettable counters to counter cells.\n"); + log("Use a target-specific 'techmap' map file to convert those cells to the actual\n"); + log("target cells.\n"); log("\n"); log(" -maxwidth N\n"); log(" Only extract counters up to N bits wide (default 64)\n"); From 0d5e9acd34b622be867db9fcc4c42934622a6130 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 10 Jul 2023 12:54:02 +0200 Subject: [PATCH 7/7] README.md: s/write_ilang/write_rtlil/ It's my understanding write_ilang is deprecated so best no to mention it in the README. --- README.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index f3a63cbec..5e5a8ec3e 100644 --- a/README.md +++ b/README.md @@ -156,9 +156,10 @@ reading and elaborating the design using the Verilog frontend: yosys> read -sv tests/simple/fiedler-cooley.v yosys> hierarchy -top up3down5 -writing the design to the console in Yosys's internal format: +writing the design to the console in the RTLIL format used by Yosys +internally: - yosys> write_ilang + yosys> write_rtlil convert processes (``always`` blocks) to netlist elements and perform some simple optimizations: