mirror of https://github.com/YosysHQ/yosys.git
rtlil: rewrite remove2() to avoid copying
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12ebdef17c
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43756559d8
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@ -2688,31 +2688,15 @@ void RTLIL::SigSpec::remove2(const pool<RTLIL::SigBit> &pattern, RTLIL::SigSpec
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other->unpack();
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other->unpack();
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}
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}
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std::vector<RTLIL::SigBit> new_bits, new_other_bits;
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for (int i = GetSize(bits_) - 1; i >= 0; i--) {
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if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
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new_bits.resize(GetSize(bits_));
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bits_.erase(bits_.begin() + i);
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if (other != NULL)
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width_--;
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new_other_bits.resize(GetSize(bits_));
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int k = 0;
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for (int i = 0; i < GetSize(bits_); i++) {
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if (bits_[i].wire != NULL && pattern.count(bits_[i]))
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continue;
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if (other != NULL)
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new_other_bits[k] = other->bits_[i];
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new_bits[k++] = bits_[i];
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}
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new_bits.resize(k);
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if (other != NULL)
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new_other_bits.resize(k);
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bits_.swap(new_bits);
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width_ = GetSize(bits_);
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if (other != NULL) {
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if (other != NULL) {
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other->bits_.swap(new_other_bits);
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other->bits_.erase(other->bits_.begin() + i);
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other->width_ = GetSize(other->bits_);
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other->width_--;
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}
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}
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}
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}
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check();
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check();
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@ -2732,26 +2716,15 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
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other->unpack();
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other->unpack();
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}
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}
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std::vector<RTLIL::SigBit> new_bits, new_other_bits;
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for (int i = GetSize(bits_) - 1; i >= 0; i--) {
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if (bits_[i].wire != NULL && pattern.count(bits_[i])) {
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new_bits.reserve(GetSize(bits_));
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bits_.erase(bits_.begin() + i);
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if (other != NULL)
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width_--;
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new_other_bits.reserve(GetSize(bits_));
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for (int i = 0; i < GetSize(bits_); i++) {
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if (bits_[i].wire != NULL && pattern.count(bits_[i]))
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continue;
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if (other != NULL)
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new_other_bits.push_back(other->bits_[i]);
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new_bits.push_back(bits_[i]);
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}
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bits_.swap(new_bits);
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width_ = GetSize(bits_);
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if (other != NULL) {
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if (other != NULL) {
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other->bits_.swap(new_other_bits);
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other->bits_.erase(other->bits_.begin() + i);
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other->width_ = GetSize(other->bits_);
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other->width_--;
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}
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}
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}
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}
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check();
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check();
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