mirror of https://github.com/YosysHQ/yosys.git
Fixed use of selection in splitnets command
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d3dc22a90f
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@ -169,7 +169,7 @@ struct SplitnetsPass : public Pass {
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{
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for (auto &w : module->wires) {
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RTLIL::Wire *wire = w.second;
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if (wire->width > 1 && (wire->port_id == 0 || flag_ports))
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if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, w.second))
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worker.splitmap[wire] = std::vector<RTLIL::SigBit>();
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}
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