mirror of https://github.com/YosysHQ/yosys.git
abc9 to recover_init by default
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3d1185b835
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416312b9ed
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@ -67,7 +67,6 @@ SigMap assign_map;
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RTLIL::Module *module;
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RTLIL::Module *module;
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std::map<RTLIL::SigBit, int> signal_map;
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std::map<RTLIL::SigBit, int> signal_map;
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std::map<RTLIL::SigBit, RTLIL::State> signal_init;
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std::map<RTLIL::SigBit, RTLIL::State> signal_init;
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bool recover_init;
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bool clk_polarity, en_polarity;
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bool clk_polarity, en_polarity;
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RTLIL::SigSpec clk_sig, en_sig;
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RTLIL::SigSpec clk_sig, en_sig;
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@ -253,7 +252,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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signal_map.clear();
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signal_map.clear();
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pi_map.clear();
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pi_map.clear();
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po_map.clear();
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po_map.clear();
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recover_init = false;
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if (clk_str != "$")
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if (clk_str != "$")
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{
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{
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@ -510,6 +508,12 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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for (int i = 0; i < GetSize(wire); i++)
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for (int i = 0; i < GetSize(wire); i++)
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output_bits.insert({wire, i});
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output_bits.insert({wire, i});
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}
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}
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auto jt = w->attributes.find("\\init");
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if (jt != w->attributes.end()) {
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auto r = remap_wire->attributes.insert(std::make_pair("\\init", jt->second));
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log_assert(r.second);
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}
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}
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}
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dict<IdString, decltype(RTLIL::Cell::parameters)> erased_boxes;
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dict<IdString, decltype(RTLIL::Cell::parameters)> erased_boxes;
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@ -649,15 +653,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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module->connect(conn);
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module->connect(conn);
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}
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}
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if (recover_init)
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for (auto wire : mapped_mod->wires()) {
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if (wire->attributes.count("\\init")) {
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Wire *w = module->wires_[remap_name(wire->name)];
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log_assert(w->attributes.count("\\init") == 0);
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w->attributes["\\init"] = wire->attributes.at("\\init");
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}
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}
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for (auto &it : cell_stats)
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for (auto &it : cell_stats)
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log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
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log("ABC RESULTS: %15s cells: %8d\n", it.first.c_str(), it.second);
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int in_wires = 0, out_wires = 0;
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int in_wires = 0, out_wires = 0;
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