riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed techmap of $reduce_xnor with multi-bit outputs

This commit is contained in:
Clifford Wolf 2013-11-07 00:58:06 +01:00
parent b41740060b
commit 404b46674b
1 changed files with 7 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
techlibs/common/stdcells.v
View File

@ -351,9 +351,15 @@ endgenerate
assign buffer[0] = A[0]; assign buffer[0] = A[0];
\$_INV_ gate_inv ( \$_INV_ gate_inv (
.A(buffer[A_WIDTH-1]), .A(buffer[A_WIDTH-1]),
.Y(Y) .Y(Y[0])
); );
generate
if (Y_WIDTH > 1) begin:V
assign Y[Y_WIDTH-1:1] = 0;
end
endgenerate
endmodule endmodule
// -------------------------------------------------------- // --------------------------------------------------------