corrections in appnote

2014-11-03 16:18:53 +01:00 · 2014-11-03 16:18:53 +01:00 · 3dd316bdc7
parent 6c6cdf736a
commit 3dd316bdc7
1 changed files with 2 additions and 1 deletions
--- a/manual/APPNOTE_012_Verilog_to_BTOR.tex
+++ b/manual/APPNOTE_012_Verilog_to_BTOR.tex
@ -150,7 +150,8 @@ endmodule

 \begin{figure}[H]
 \begin{lstlisting}[language=Verilog]
-module test(input clk, input rst, output y);
+module test(input clk, input rst, output y, 
+  output safety1);
 reg [2:0] state;
 output safety1;
 always @(posedge clk) begin