diff --git a/manual/APPNOTE_012_Verilog_to_BTOR.tex b/manual/APPNOTE_012_Verilog_to_BTOR.tex
index 7cd73943c..270ccacdd 100644
--- a/manual/APPNOTE_012_Verilog_to_BTOR.tex
+++ b/manual/APPNOTE_012_Verilog_to_BTOR.tex
@@ -150,7 +150,8 @@ endmodule
 
 \begin{figure}[H]
 \begin{lstlisting}[language=Verilog]
-module test(input clk, input rst, output y);
+module test(input clk, input rst, output y, 
+  output safety1);
 reg [2:0] state;
 output safety1;
 always @(posedge clk) begin