riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added "test_cell -s <seed>"

This commit is contained in:
Clifford Wolf 2014-08-16 19:44:31 +02:00
parent 83e2698e10
commit 3b9157f9a6
1 changed files with 17 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
passes/tests/test_cell.cc
View File

@ -21,12 +21,13 @@
#include "kernel/yosys.h" #include "kernel/yosys.h"
#include <algorithm> #include <algorithm>
static uint32_t xorshift32_state = 123456789;
static uint32_t xorshift32(uint32_t limit) { static uint32_t xorshift32(uint32_t limit) {
static uint32_t x = 123456789; xorshift32_state ^= xorshift32_state << 13;
x ^= x << 13; xorshift32_state ^= xorshift32_state >> 17;
x ^= x >> 17; xorshift32_state ^= xorshift32_state << 5;
x ^= x << 5; return xorshift32_state % limit;
return x % limit;
} }
static void create_gold_module(RTLIL::Design *design, std::string cell_type, std::string cell_type_flags) static void create_gold_module(RTLIL::Design *design, std::string cell_type, std::string cell_type_flags)
@ -94,6 +95,9 @@ struct TestCellPass : public Pass {
log(" -n {integer}\n"); log(" -n {integer}\n");
log(" create this number of cell instances and test them (default = 100).\n"); log(" create this number of cell instances and test them (default = 100).\n");
log("\n"); log("\n");
log(" -s {positive_integer}\n");
log(" use this value as rng seed value (default = unix time).\n");
log("\n");
log(" -f {ilang_file}\n"); log(" -f {ilang_file}\n");
log(" don't generate circuits. instead load the specified ilang file.\n"); log(" don't generate circuits. instead load the specified ilang file.\n");
log("\n"); log("\n");
@ -106,6 +110,7 @@ struct TestCellPass : public Pass {
int num_iter = 100; int num_iter = 100;
std::string techmap_cmd = "techmap -assert"; std::string techmap_cmd = "techmap -assert";
std::string ilang_file; std::string ilang_file;
xorshift32_state = 0;
int argidx; int argidx;
for (argidx = 1; argidx < SIZE(args); argidx++) for (argidx = 1; argidx < SIZE(args); argidx++)
@ -114,6 +119,10 @@ struct TestCellPass : public Pass {
num_iter = atoi(args[++argidx].c_str()); num_iter = atoi(args[++argidx].c_str());
continue; continue;
} }
if (args[argidx] == "-s" && argidx+1 < SIZE(args)) {
xorshift32_state = atoi(args[++argidx].c_str());
continue;
}
if (args[argidx] == "-map" && argidx+1 < SIZE(args)) { if (args[argidx] == "-map" && argidx+1 < SIZE(args)) {
techmap_cmd += " -map " + args[++argidx]; techmap_cmd += " -map " + args[++argidx];
continue; continue;
@ -126,6 +135,9 @@ struct TestCellPass : public Pass {
break; break;
} }
if (xorshift32_state == 0)
xorshift32_state = time(NULL);
std::map<std::string, std::string> cell_types; std::map<std::string, std::string> cell_types;
std::vector<std::string> selected_cell_types; std::vector<std::string> selected_cell_types;