mirror of https://github.com/YosysHQ/yosys.git
Add initial NanoXplore pass
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OBJS += techlibs/nanoxplore/synth_nanoxplore.o
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# Techmap
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v))
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$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v))
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`default_nettype none
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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(* force_downto *)
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};
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NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),
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.I1(1'b0), .I2(1'b0), .I3(1'b0), .I4(A[0]));
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end else
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if (WIDTH == 2) begin
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localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}};
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NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),
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.I1(1'b0), .I2(1'b0), .I3(A[0]), .I4(A[1]));
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end else
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if (WIDTH == 3) begin
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localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}};
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NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y),
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.I1(1'b0), .I2(A[0]), .I3(A[1]), .I4(A[2]));
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end else
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if (WIDTH == 4) begin
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NX_LUT #(.lut_table(LUT)) _TECHMAP_REPLACE_ (.O(Y),
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.I1(A[0]), .I2(A[1]), .I3(A[2]), .I4(A[3]));
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end else begin
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wire _TECHMAP_FAIL_ = 1;
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end
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endgenerate
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endmodule
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module NX_LUT(input I1, I2, I3, I4, output O);
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parameter lut_table = 16'h0000;
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wire [7:0] s1 = I4 ? lut_table[15:8] : lut_table[7:0];
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wire [3:0] s2 = I3 ? s1[7:4] : s1[3:0];
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wire [1:0] s3 = I2 ? s2[3:2] : s2[1:0];
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assign O = I1 ? s3[1] : s3[0];
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endmodule
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2024 Hannah Ravensloft <lofty@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SynthNanoXplorePass : public ScriptPass
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{
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SynthNanoXplorePass() : ScriptPass("synth_nanoxplore", "synthesis for NanoXplore FPGAs") { }
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void on_register() override
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{
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RTLIL::constpad["synth_nanoxplore.abc9.W"] = "300";
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}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth_nanoxplore [options]\n");
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log("\n");
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log("This command runs synthesis for NanoXplore FPGAs.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module\n");
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log("\n");
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log(" -json <file>\n");
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log(" write the design to the specified JSON file. writing of an output file\n");
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log(" is omitted if this parameter is not specified.\n");
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log("\n");
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log(" -run <from_label>:<to_label>\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -noflatten\n");
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log(" do not flatten design before synthesis\n");
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log("\n");
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log(" -abc9\n");
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log(" use new ABC9 flow (EXPERIMENTAL)\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_opt, json_file;
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bool flatten, abc9;
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void clear_flags() override
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{
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top_opt = "-auto-top";
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json_file = "";
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flatten = true;
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abc9 = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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string run_from, run_to;
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clear_flags();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-top" && argidx+1 < args.size()) {
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top_opt = "-top " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-json" && argidx+1 < args.size()) {
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json_file = args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx+1 < args.size()) {
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size_t pos = args[argidx+1].find(':');
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if (pos == std::string::npos)
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break;
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos+1);
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continue;
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}
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if (args[argidx] == "-flatten") {
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flatten = true;
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continue;
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}
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if (args[argidx] == "-noflatten") {
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flatten = false;
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continue;
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}
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if (args[argidx] == "-abc9") {
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abc9 = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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log_header(design, "Executing SYNTH_NANOXPLORE pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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void script() override
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{
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if (check_label("begin"))
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{
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run("read_verilog -lib -specify +/nanoxplore/cells_sim.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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}
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if (check_label("coarse"))
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{
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run("proc");
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if (flatten || help_mode)
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run("flatten", "(skip if -noflatten)");
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run("tribuf -logic");
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run("deminout");
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run("opt_expr");
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run("opt_clean");
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run("check");
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run("opt -nodffe -nosdff");
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run("fsm");
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run("opt");
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run("wreduce");
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run("peepopt");
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run("opt_clean");
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run("share");
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run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4");
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run("opt_expr");
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run("opt_clean");
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run("alumacc");
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run("opt");
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run("memory -nomap");
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run("opt_clean");
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}
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if (check_label("map_ram"))
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{
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}
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if (check_label("map_ffram"))
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{
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run("opt -fast -mux_undef -undriven -fine");
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run("memory_map");
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run("opt -undriven -fine -mux_undef");
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}
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if (check_label("map_gates"))
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{
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run("techmap");
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run("opt -fast");
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}
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if (check_label("map_ffs"))
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{
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run("techmap");
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run("dfflegalize -cell $_DFF_?P?_ 0 -cell $_ALDFF_?P_ 0 -cell $_SDFF_?P?_ 0");
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run("techmap -map +/nanoxplore/cells_map.v");
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run("opt_expr -undriven -mux_undef");
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run("clean -purge");
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}
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if (check_label("map_luts"))
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{
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if (abc9) {
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std::string abc9_opts = " -maxlut 4";
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std::string k = "synth_nanoxplore.abc9.W";
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if (active_design && active_design->scratchpad.count(k))
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abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str());
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else
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abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str());
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run("abc9" + abc9_opts);
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} else {
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std::string abc_args = " -dress";
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abc_args += " -lut 4";
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run("abc" + abc_args);
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}
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run("techmap -map +/nanoxplore/cells_map.v t:$lut");
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run("opt -fast");
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run("clean");
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}
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if (check_label("check"))
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{
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run("autoname");
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run("hierarchy -check");
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run("stat");
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run("check -noinit");
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run("blackbox =A:whitebox");
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}
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if (check_label("json"))
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{
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if (!json_file.empty() || help_mode)
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run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
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}
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}
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} SynthNanoXplorePass;
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PRIVATE_NAMESPACE_END
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