diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc new file mode 100644 index 000000000..7e2923c40 --- /dev/null +++ b/techlibs/nanoxplore/Makefile.inc @@ -0,0 +1,6 @@ + +OBJS += techlibs/nanoxplore/synth_nanoxplore.o + +# Techmap +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_map.v)) +$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_sim.v)) diff --git a/techlibs/nanoxplore/cells_map.v b/techlibs/nanoxplore/cells_map.v new file mode 100644 index 000000000..4a83fafc2 --- /dev/null +++ b/techlibs/nanoxplore/cells_map.v @@ -0,0 +1,34 @@ +`default_nettype none + +module \$lut (A, Y); + parameter WIDTH = 0; + parameter LUT = 0; + + (* force_downto *) + input [WIDTH-1:0] A; + output Y; + + generate + if (WIDTH == 1) begin + localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}}; + NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y), + .I1(1'b0), .I2(1'b0), .I3(1'b0), .I4(A[0])); + end else + if (WIDTH == 2) begin + localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[2]}}, {4{LUT[1]}}, {4{LUT[0]}}}; + NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y), + .I1(1'b0), .I2(1'b0), .I3(A[0]), .I4(A[1])); + end else + if (WIDTH == 3) begin + localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[6]}}, {2{LUT[5]}}, {2{LUT[4]}}, {2{LUT[3]}}, {2{LUT[2]}}, {2{LUT[1]}}, {2{LUT[0]}}}; + NX_LUT #(.lut_table(INIT)) _TECHMAP_REPLACE_ (.O(Y), + .I1(1'b0), .I2(A[0]), .I3(A[1]), .I4(A[2])); + end else + if (WIDTH == 4) begin + NX_LUT #(.lut_table(LUT)) _TECHMAP_REPLACE_ (.O(Y), + .I1(A[0]), .I2(A[1]), .I3(A[2]), .I4(A[3])); + end else begin + wire _TECHMAP_FAIL_ = 1; + end + endgenerate +endmodule diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v new file mode 100644 index 000000000..d665e0f89 --- /dev/null +++ b/techlibs/nanoxplore/cells_sim.v @@ -0,0 +1,10 @@ +module NX_LUT(input I1, I2, I3, I4, output O); + +parameter lut_table = 16'h0000; + +wire [7:0] s1 = I4 ? lut_table[15:8] : lut_table[7:0]; +wire [3:0] s2 = I3 ? s1[7:4] : s1[3:0]; +wire [1:0] s3 = I2 ? s2[3:2] : s2[1:0]; +assign O = I1 ? s3[1] : s3[0]; + +endmodule diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc new file mode 100644 index 000000000..3d8a34c06 --- /dev/null +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -0,0 +1,228 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2024 Hannah Ravensloft + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/celltypes.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct SynthNanoXplorePass : public ScriptPass +{ + SynthNanoXplorePass() : ScriptPass("synth_nanoxplore", "synthesis for NanoXplore FPGAs") { } + + void on_register() override + { + RTLIL::constpad["synth_nanoxplore.abc9.W"] = "300"; + } + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" synth_nanoxplore [options]\n"); + log("\n"); + log("This command runs synthesis for NanoXplore FPGAs.\n"); + log("\n"); + log(" -top \n"); + log(" use the specified module as top module\n"); + log("\n"); + log(" -json \n"); + log(" write the design to the specified JSON file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); + log("\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); + log("\n"); + log(" -abc9\n"); + log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log("\n"); + log("\n"); + log("The following commands are executed by this synthesis command:\n"); + help_script(); + log("\n"); + } + + string top_opt, json_file; + bool flatten, abc9; + + void clear_flags() override + { + top_opt = "-auto-top"; + json_file = ""; + flatten = true; + abc9 = false; + } + + void execute(std::vector args, RTLIL::Design *design) override + { + string run_from, run_to; + clear_flags(); + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-top" && argidx+1 < args.size()) { + top_opt = "-top " + args[++argidx]; + continue; + } + if (args[argidx] == "-json" && argidx+1 < args.size()) { + json_file = args[++argidx]; + continue; + } + if (args[argidx] == "-run" && argidx+1 < args.size()) { + size_t pos = args[argidx+1].find(':'); + if (pos == std::string::npos) + break; + run_from = args[++argidx].substr(0, pos); + run_to = args[argidx].substr(pos+1); + continue; + } + if (args[argidx] == "-flatten") { + flatten = true; + continue; + } + if (args[argidx] == "-noflatten") { + flatten = false; + continue; + } + if (args[argidx] == "-abc9") { + abc9 = true; + continue; + } + break; + } + extra_args(args, argidx, design); + + if (!design->full_selection()) + log_cmd_error("This command only operates on fully selected designs!\n"); + + log_header(design, "Executing SYNTH_NANOXPLORE pass.\n"); + log_push(); + + run_script(design, run_from, run_to); + + log_pop(); + } + + void script() override + { + if (check_label("begin")) + { + run("read_verilog -lib -specify +/nanoxplore/cells_sim.v"); + run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); + } + + if (check_label("coarse")) + { + run("proc"); + if (flatten || help_mode) + run("flatten", "(skip if -noflatten)"); + run("tribuf -logic"); + run("deminout"); + run("opt_expr"); + run("opt_clean"); + run("check"); + run("opt -nodffe -nosdff"); + run("fsm"); + run("opt"); + run("wreduce"); + run("peepopt"); + run("opt_clean"); + run("share"); + run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); + run("opt_expr"); + run("opt_clean"); + run("alumacc"); + run("opt"); + run("memory -nomap"); + run("opt_clean"); + } + + if (check_label("map_ram")) + { + } + + if (check_label("map_ffram")) + { + run("opt -fast -mux_undef -undriven -fine"); + run("memory_map"); + run("opt -undriven -fine -mux_undef"); + } + + if (check_label("map_gates")) + { + run("techmap"); + run("opt -fast"); + } + + if (check_label("map_ffs")) + { + run("techmap"); + run("dfflegalize -cell $_DFF_?P?_ 0 -cell $_ALDFF_?P_ 0 -cell $_SDFF_?P?_ 0"); + run("techmap -map +/nanoxplore/cells_map.v"); + run("opt_expr -undriven -mux_undef"); + run("clean -purge"); + } + + if (check_label("map_luts")) + { + if (abc9) { + std::string abc9_opts = " -maxlut 4"; + std::string k = "synth_nanoxplore.abc9.W"; + if (active_design && active_design->scratchpad.count(k)) + abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); + else + abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); + run("abc9" + abc9_opts); + } else { + std::string abc_args = " -dress"; + abc_args += " -lut 4"; + run("abc" + abc_args); + } + run("techmap -map +/nanoxplore/cells_map.v t:$lut"); + run("opt -fast"); + run("clean"); + } + + if (check_label("check")) + { + run("autoname"); + run("hierarchy -check"); + run("stat"); + run("check -noinit"); + run("blackbox =A:whitebox"); + } + + if (check_label("json")) + { + if (!json_file.empty() || help_mode) + run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); + } + } +} SynthNanoXplorePass; + +PRIVATE_NAMESPACE_END