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simlib: Fix wide $bmux and avoid iverilog warnings

This commit is contained in:
Jannis Harder 2022-11-11 14:31:39 +01:00
parent b982ab4f59
commit 39ac113402
1 changed files with 2 additions and 2 deletions
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4
techlibs/common/simlib.v
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@ -1300,11 +1300,11 @@ wire [WIDTH-1:0] bm0_out, bm1_out;
generate generate
if (S_WIDTH > 1) begin:muxlogic if (S_WIDTH > 1) begin:muxlogic
\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A), .S(S[S_WIDTH-2:0]), .Y(bm0_out)); \$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A[(WIDTH << (S_WIDTH - 1))-1:0]), .S(S[S_WIDTH-2:0]), .Y(bm0_out));
\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm1 (.A(A[(WIDTH << S_WIDTH)-1:WIDTH << (S_WIDTH - 1)]), .S(S[S_WIDTH-2:0]), .Y(bm1_out)); \$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm1 (.A(A[(WIDTH << S_WIDTH)-1:WIDTH << (S_WIDTH - 1)]), .S(S[S_WIDTH-2:0]), .Y(bm1_out));
assign Y = S[S_WIDTH-1] ? bm1_out : bm0_out; assign Y = S[S_WIDTH-1] ? bm1_out : bm0_out;
end else if (S_WIDTH == 1) begin:simple end else if (S_WIDTH == 1) begin:simple
assign Y = S ? A[1] : A[0]; assign Y = S ? A[2*WIDTH-1:WIDTH] : A[WIDTH-1:0];
end else begin:passthru end else begin:passthru
assign Y = A; assign Y = A;
end end