diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index b5e437d90..498cc27c2 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1300,11 +1300,11 @@ wire [WIDTH-1:0] bm0_out, bm1_out;
 
 generate
 	if (S_WIDTH > 1) begin:muxlogic
-		\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A), .S(S[S_WIDTH-2:0]), .Y(bm0_out));
+		\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm0 (.A(A[(WIDTH << (S_WIDTH - 1))-1:0]), .S(S[S_WIDTH-2:0]), .Y(bm0_out));
 		\$bmux #(.WIDTH(WIDTH), .S_WIDTH(S_WIDTH-1)) bm1 (.A(A[(WIDTH << S_WIDTH)-1:WIDTH << (S_WIDTH - 1)]), .S(S[S_WIDTH-2:0]), .Y(bm1_out));
 		assign Y = S[S_WIDTH-1] ? bm1_out : bm0_out;
 	end else if (S_WIDTH == 1) begin:simple
-		assign Y = S ? A[1] : A[0];
+		assign Y = S ? A[2*WIDTH-1:WIDTH] : A[WIDTH-1:0];
 	end else begin:passthru
 		assign Y = A;
 	end