mirror of https://github.com/YosysHQ/yosys.git
Added sat -show-inputs and -show-outputs
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@ -693,6 +693,9 @@ struct SatPass : public Pass {
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log(" show the model for the specified signal. if no -show option is\n");
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log(" show the model for the specified signal. if no -show option is\n");
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log(" passed then a set of signals to be shown is automatically selected.\n");
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log(" passed then a set of signals to be shown is automatically selected.\n");
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log("\n");
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log("\n");
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log(" -show-inputs, -show-outputs\n");
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log(" add all module input (output) ports to the list of shown signals\n");
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log("\n");
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log(" -ignore_div_by_zero\n");
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log(" -ignore_div_by_zero\n");
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log(" ignore all solutions that involve a division by zero\n");
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log(" ignore all solutions that involve a division by zero\n");
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log("\n");
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log("\n");
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@ -758,7 +761,7 @@ struct SatPass : public Pass {
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int loopcount = 0, seq_len = 0, maxsteps = 0, timeout = 0;
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int loopcount = 0, seq_len = 0, maxsteps = 0, timeout = 0;
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bool verify = false, fail_on_timeout = false, enable_undef = false, set_def_inputs = false;
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bool verify = false, fail_on_timeout = false, enable_undef = false, set_def_inputs = false;
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bool ignore_div_by_zero = false, set_init_undef = false, max_undef = false;
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bool ignore_div_by_zero = false, set_init_undef = false, max_undef = false;
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bool tempinduct = false, prove_asserts = false;
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bool tempinduct = false, prove_asserts = false, show_inputs = false, show_outputs = false;
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log_header("Executing SAT pass (solving SAT problems in the circuit).\n");
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log_header("Executing SAT pass (solving SAT problems in the circuit).\n");
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@ -898,6 +901,14 @@ struct SatPass : public Pass {
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shows.push_back(args[++argidx]);
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shows.push_back(args[++argidx]);
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continue;
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continue;
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}
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}
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if (args[argidx] == "-show-inputs") {
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show_inputs = true;
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continue;
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}
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if (args[argidx] == "-show-outputs") {
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show_outputs = true;
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continue;
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}
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break;
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break;
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}
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}
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extra_args(args, argidx, design);
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extra_args(args, argidx, design);
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@ -928,6 +939,18 @@ struct SatPass : public Pass {
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sets_def.push_back(it.second->name);
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sets_def.push_back(it.second->name);
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}
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}
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if (show_inputs) {
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for (auto &it : module->wires)
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if (it.second->port_input)
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shows.push_back(it.second->name);
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}
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if (show_outputs) {
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for (auto &it : module->wires)
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if (it.second->port_output)
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shows.push_back(it.second->name);
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}
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if (tempinduct)
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if (tempinduct)
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{
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{
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if (loopcount > 0 || max_undef)
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if (loopcount > 0 || max_undef)
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