mirror of https://github.com/YosysHQ/yosys.git
Fix "read_blif -wideports" handling of cells with wide ports
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26766da343
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@ -67,7 +67,7 @@ static std::pair<RTLIL::IdString, int> wideports_split(std::string name)
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pos = i;
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pos = i;
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else if (name[i] < '0' || name[i] > '9')
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else if (name[i] < '0' || name[i] > '9')
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pos = -1;
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pos = -1;
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else if (i == pos+1 && name[i] == '0')
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else if (i == pos+1 && name[i] == '0' && name[i+1] != ']')
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pos = -1;
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pos = -1;
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}
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}
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@ -345,12 +345,42 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name, bo
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IdString celltype = RTLIL::escape_id(p);
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IdString celltype = RTLIL::escape_id(p);
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RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);
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RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);
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while ((p = strtok(NULL, " \t\r\n")) != NULL) {
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dict<RTLIL::IdString, dict<int, SigBit>> cell_wideports_cache;
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while ((p = strtok(NULL, " \t\r\n")) != NULL)
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{
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char *q = strchr(p, '=');
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char *q = strchr(p, '=');
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if (q == NULL || !q[0])
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if (q == NULL || !q[0])
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goto error;
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goto error;
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*(q++) = 0;
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*(q++) = 0;
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cell->setPort(RTLIL::escape_id(p), *q ? blif_wire(q) : SigSpec());
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if (wideports) {
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std::pair<RTLIL::IdString, int> wp = wideports_split(p);
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if (wp.second > 0)
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cell_wideports_cache[wp.first][wp.second-1] = blif_wire(q);
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else
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cell->setPort(RTLIL::escape_id(p), *q ? blif_wire(q) : SigSpec());
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} else {
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cell->setPort(RTLIL::escape_id(p), *q ? blif_wire(q) : SigSpec());
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}
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}
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for (auto &it : cell_wideports_cache)
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{
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int width = 0;
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for (auto &b : it.second)
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width = std::max(width, b.first + 1);
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SigSpec sig;
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for (int i = 0; i < width; i++) {
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if (it.second.count(i))
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sig.append(it.second.at(i));
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else
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sig.append(module->addWire(NEW_ID));
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}
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cell->setPort(it.first, sig);
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}
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}
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obj_attributes = &cell->attributes;
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obj_attributes = &cell->attributes;
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