riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fixed a few VS warnings

This commit is contained in:
Clifford Wolf 2014-10-17 06:02:38 +02:00
parent 18cb8b4636
commit 34caeeb4f3
3 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
kernel/log.h
View File

@ -181,7 +181,7 @@ struct PerformanceTimer
} }
float sec() const { float sec() const {
return total_ns * 1e-9; return total_ns * 1e-9f;
} }
#else #else
static int64_t query() { return 0; } static int64_t query() { return 0; }

2
kernel/rtlil.h
View File

@ -898,7 +898,7 @@ struct RTLIL::SigBit
SigBit() : wire(NULL), data(RTLIL::State::S0) { } SigBit() : wire(NULL), data(RTLIL::State::S0) { }
SigBit(RTLIL::State bit) : wire(NULL), data(bit) { } SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }
SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); } SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }
SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire); } SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }
SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; } SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }
SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; } SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data[index]; }
SigBit(const RTLIL::SigSpec &sig); SigBit(const RTLIL::SigSpec &sig);

2
kernel/satgen.h
View File

@ -107,7 +107,7 @@ struct SatGen
{ {
log_assert(timestep != 0); log_assert(timestep != 0);
std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
return imported_signals[pf].count(bit); return imported_signals[pf].count(bit) != 0;
} }
void getAsserts(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1) void getAsserts(RTLIL::SigSpec &sig_a, RTLIL::SigSpec &sig_en, int timestep = -1)