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Make liberal use of IdString.in()

This commit is contained in:
Eddie Hung 2019-08-06 16:18:18 -07:00
parent 43081337fa
commit 3486235338
18 changed files with 45 additions and 51 deletions
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2
backends/smt2/smt2.cc
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@ -601,7 +601,7 @@ struct Smt2Worker
if (cell->type == "$logic_and") return export_reduce(cell, "(and (or A) (or B))", false); if (cell->type == "$logic_and") return export_reduce(cell, "(and (or A) (or B))", false);
if (cell->type == "$logic_or") return export_reduce(cell, "(or A B)", false); if (cell->type == "$logic_or") return export_reduce(cell, "(or A B)", false);
if (cell->type == "$mux" || cell->type == "$pmux") if (cell->type.in("$mux", "$pmux"))
{ {
int width = GetSize(cell->getPort("\\Y")); int width = GetSize(cell->getPort("\\Y"));
std::string processed_expr = get_bv(cell->getPort("\\A")); std::string processed_expr = get_bv(cell->getPort("\\A"));

2
backends/verilog/verilog_backend.cc
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@ -949,7 +949,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true; return true;
} }
if (cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffe") if (cell->type.in("$dff", "$adff", "$dffe"))
{ {
RTLIL::SigSpec sig_clk, sig_arst, sig_en, val_arst; RTLIL::SigSpec sig_clk, sig_arst, sig_en, val_arst;
bool pol_clk, pol_arst = false, pol_en = false; bool pol_clk, pol_arst = false, pol_en = false;

2
kernel/rtlil.cc
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@ -940,7 +940,7 @@ namespace {
return; return;
} }
if (cell->type == "$logic_and" || cell->type == "$logic_or") { if (cell->type.in("$logic_and", "$logic_or")) {
param_bool("\\A_SIGNED"); param_bool("\\A_SIGNED");
param_bool("\\B_SIGNED"); param_bool("\\B_SIGNED");
port("\\A", param("\\A_WIDTH")); port("\\A", param("\\A_WIDTH"));

2
passes/fsm/fsm_expand.cc
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@ -50,7 +50,7 @@ struct FsmExpand
if (full_mode || cell->type == "$_MUX_") if (full_mode || cell->type == "$_MUX_")
return true; return true;
if (cell->type == "$mux" || cell->type == "$pmux") if (cell->type.in("$mux", "$pmux"))
if (cell->getPort("\\A").size() < 2) if (cell->getPort("\\A").size() < 2)
return true; return true;

2
passes/memory/memory_dff.cc
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@ -262,7 +262,7 @@ struct MemoryDffWorker
mux_cells_a[sigmap(cell->getPort("\\A"))] = cell; mux_cells_a[sigmap(cell->getPort("\\A"))] = cell;
mux_cells_b[sigmap(cell->getPort("\\B"))] = cell; mux_cells_b[sigmap(cell->getPort("\\B"))] = cell;
} }
if (cell->type == "$not" || cell->type == "$_NOT_" || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) { if (cell->type.in("$not", "$_NOT_") || (cell->type == "$logic_not" && GetSize(cell->getPort("\\A")) == 1)) {
SigSpec sig_a = cell->getPort("\\A"); SigSpec sig_a = cell->getPort("\\A");
SigSpec sig_y = cell->getPort("\\Y"); SigSpec sig_y = cell->getPort("\\Y");
if (cell->type == "$not") if (cell->type == "$not")

6
passes/memory/memory_share.cc
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@ -155,7 +155,7 @@ struct MemoryShareWorker
{ {
bool ignore_data_port = false; bool ignore_data_port = false;
if (cell->type == "$mux" || cell->type == "$pmux") if (cell->type.in("$mux", "$pmux"))
{ {
std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A")); std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort("\\A"));
std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B")); std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort("\\B"));
@ -173,7 +173,7 @@ struct MemoryShareWorker
continue; continue;
} }
if ((cell->type == "$memwr" || cell->type == "$memrd") && if (cell->type.in("$memwr", "$memrd") &&
cell->parameters.at("\\MEMID").decode_string() == memid) cell->parameters.at("\\MEMID").decode_string() == memid)
ignore_data_port = true; ignore_data_port = true;
@ -690,7 +690,7 @@ struct MemoryShareWorker
sigmap_xmux.add(cell->getPort("\\Y"), sig_a); sigmap_xmux.add(cell->getPort("\\Y"), sig_a);
} }
if (cell->type == "$mux" || cell->type == "$pmux") if (cell->type.in("$mux", "$pmux"))
{ {
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y")); std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort("\\Y"));
for (int i = 0; i < int(sig_y.size()); i++) for (int i = 0; i < int(sig_y.size()); i++)

8
passes/opt/opt_merge.cc
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@ -94,8 +94,8 @@ struct OptMergeWorker
const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections(); const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn; dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$mul" || if (cell->type.in("$and", "$or", "$xor", "$xnor", "$add", "$mul",
cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") { "$logic_and", "$logic_or", "$_AND_", "$_OR_", "$_XOR_")) {
alt_conn = *conn; alt_conn = *conn;
if (assign_map(alt_conn.at("\\A")) < assign_map(alt_conn.at("\\B"))) { if (assign_map(alt_conn.at("\\A")) < assign_map(alt_conn.at("\\B"))) {
alt_conn["\\A"] = conn->at("\\B"); alt_conn["\\A"] = conn->at("\\B");
@ -103,13 +103,13 @@ struct OptMergeWorker
} }
conn = &alt_conn; conn = &alt_conn;
} else } else
if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor") { if (cell->type.in("$reduce_xor", "$reduce_xnor")) {
alt_conn = *conn; alt_conn = *conn;
assign_map.apply(alt_conn.at("\\A")); assign_map.apply(alt_conn.at("\\A"));
alt_conn.at("\\A").sort(); alt_conn.at("\\A").sort();
conn = &alt_conn; conn = &alt_conn;
} else } else
if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_bool") { if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool")) {
alt_conn = *conn; alt_conn = *conn;
assign_map.apply(alt_conn.at("\\A")); assign_map.apply(alt_conn.at("\\A"));
alt_conn.at("\\A").sort_and_unify(); alt_conn.at("\\A").sort_and_unify();

2
passes/opt/opt_muxtree.cc
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@ -84,7 +84,7 @@ struct OptMuxtreeWorker
// .const_deactivated // .const_deactivated
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (cell->type == "$mux" || cell->type == "$pmux") if (cell->type.in("$mux", "$pmux"))
{ {
RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_b = cell->getPort("\\B"); RTLIL::SigSpec sig_b = cell->getPort("\\B");

6
passes/opt/opt_rmdff.cc
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@ -71,7 +71,7 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
pol_set = cell->type[12] == 'P' ? State::S1 : State::S0; pol_set = cell->type[12] == 'P' ? State::S1 : State::S0;
pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0; pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0;
} else } else
if (cell->type == "$dffsr" || cell->type == "$dlatchsr") { if (cell->type.in("$dffsr", "$dlatchsr")) {
pol_set = cell->parameters["\\SET_POLARITY"].as_bool() ? State::S1 : State::S0; pol_set = cell->parameters["\\SET_POLARITY"].as_bool() ? State::S1 : State::S0;
pol_clr = cell->parameters["\\CLR_POLARITY"].as_bool() ? State::S1 : State::S0; pol_clr = cell->parameters["\\CLR_POLARITY"].as_bool() ? State::S1 : State::S0;
} else } else
@ -137,7 +137,7 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
return true; return true;
} }
if (cell->type == "$dffsr" || cell->type == "$dlatchsr") if (cell->type.in("$dffsr", "$dlatchsr"))
{ {
cell->setParam("\\WIDTH", GetSize(sig_d)); cell->setParam("\\WIDTH", GetSize(sig_d));
cell->setPort("\\SET", sig_set); cell->setPort("\\SET", sig_set);
@ -624,7 +624,7 @@ struct OptRmdffPass : public Pass {
} }
} }
if (cell->type == "$mux" || cell->type == "$pmux") { if (cell->type.in("$mux", "$pmux")) {
if (cell->getPort("\\A").size() == cell->getPort("\\B").size()) if (cell->getPort("\\A").size() == cell->getPort("\\B").size())
mux_drivers.insert(assign_map(cell->getPort("\\Y")), cell); mux_drivers.insert(assign_map(cell->getPort("\\Y")), cell);
continue; continue;

4
passes/opt/share.cc
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@ -376,13 +376,13 @@ struct ShareWorker
continue; continue;
} }
if (cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod") { if (cell->type.in("$mul", "$div", "$mod")) {
if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 4) if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 4)
shareable_cells.insert(cell); shareable_cells.insert(cell);
continue; continue;
} }
if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") { if (cell->type.in("$shl", "$shr", "$sshl", "$sshr")) {
if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 8) if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 8)
shareable_cells.insert(cell); shareable_cells.insert(cell);
continue; continue;

4
passes/proc/proc_arst.cc
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@ -55,7 +55,7 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref,
return check_signal(mod, cell->getPort("\\A"), ref, polarity); return check_signal(mod, cell->getPort("\\A"), ref, polarity);
} }
if ((cell->type == "$eq" || cell->type == "$eqx") && cell->getPort("\\Y") == signal) { if (cell->type.in("$eq", "$eqx") && cell->getPort("\\Y") == signal) {
if (cell->getPort("\\A").is_fully_const()) { if (cell->getPort("\\A").is_fully_const()) {
if (!cell->getPort("\\A").as_bool()) if (!cell->getPort("\\A").as_bool())
polarity = !polarity; polarity = !polarity;
@ -68,7 +68,7 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref,
} }
} }
if ((cell->type == "$ne" || cell->type == "$nex") && cell->getPort("\\Y") == signal) { if (cell->type.in("$ne", "$nex") && cell->getPort("\\Y") == signal) {
if (cell->getPort("\\A").is_fully_const()) { if (cell->getPort("\\A").is_fully_const()) {
if (cell->getPort("\\A").as_bool()) if (cell->getPort("\\A").as_bool())
polarity = !polarity; polarity = !polarity;

16
passes/techmap/abc.cc
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@ -166,7 +166,7 @@ void mark_port(RTLIL::SigSpec sig)
void extract_cell(RTLIL::Cell *cell, bool keepff) void extract_cell(RTLIL::Cell *cell, bool keepff)
{ {
if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_") if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
{ {
if (clk_polarity != (cell->type == "$_DFF_P_")) if (clk_polarity != (cell->type == "$_DFF_P_"))
return; return;
@ -177,11 +177,11 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
goto matching_dff; goto matching_dff;
} }
if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_") if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_"))
{ {
if (clk_polarity != (cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_")) if (clk_polarity != cell->type.in("$_DFFE_PN_", "$_DFFE_PP_"))
return; return;
if (en_polarity != (cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_")) if (en_polarity != cell->type.in("$_DFFE_NP_", "$_DFFE_PP_"))
return; return;
if (clk_sig != assign_map(cell->getPort("\\C"))) if (clk_sig != assign_map(cell->getPort("\\C")))
return; return;
@ -1824,15 +1824,15 @@ struct AbcPass : public Pass {
} }
} }
if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_") if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
{ {
key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec()); key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
} }
else else
if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_") if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_" "$_DFFE_PN_", "$_DFFE_PP_"))
{ {
bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_"; bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_");
bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_"; bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_");
key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E"))); key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
} }
else else

8
passes/techmap/abc9.cc
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@ -1137,15 +1137,15 @@ struct Abc9Pass : public Pass {
} }
} }
if (cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_") if (cell->type.in("$_DFF_N_", "$_DFF_P_"))
{ {
key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec()); key = clkdomain_t(cell->type == "$_DFF_P_", assign_map(cell->getPort("\\C")), true, RTLIL::SigSpec());
} }
else else
if (cell->type == "$_DFFE_NN_" || cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_") if (cell->type.in("$_DFFE_NN_", "$_DFFE_NP_", "$_DFFE_PN_", "$_DFFE_PP_"))
{ {
bool this_clk_pol = cell->type == "$_DFFE_PN_" || cell->type == "$_DFFE_PP_"; bool this_clk_pol = cell->type.in("$_DFFE_PN_", "$_DFFE_PP_");
bool this_en_pol = cell->type == "$_DFFE_NP_" || cell->type == "$_DFFE_PP_"; bool this_en_pol = cell->type.in("$_DFFE_NP_", "$_DFFE_PP_");
key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E"))); key = clkdomain_t(this_clk_pol, assign_map(cell->getPort("\\C")), this_en_pol, assign_map(cell->getPort("\\E")));
} }
else else

2
passes/techmap/aigmap.cc
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@ -66,7 +66,7 @@ struct AigmapPass : public Pass {
{ {
Aig aig(cell); Aig aig(cell);
if (cell->type == "$_AND_" || cell->type == "$_NOT_") if (cell->type.in("$_AND_", "$_NOT_"))
aig.name.clear(); aig.name.clear();
if (nand_mode && cell->type == "$_NAND_") if (nand_mode && cell->type == "$_NAND_")

2
passes/techmap/deminout.cc
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@ -85,7 +85,7 @@ struct DeminoutPass : public Pass {
if (conn.first == "\\Y" && cell->type.in("$mux", "$pmux", "$_MUX_", "$_TBUF_", "$tribuf")) if (conn.first == "\\Y" && cell->type.in("$mux", "$pmux", "$_MUX_", "$_TBUF_", "$tribuf"))
{ {
bool tribuf = (cell->type == "$_TBUF_" || cell->type == "$tribuf"); bool tribuf = cell->type.in("$_TBUF_", "$tribuf");
if (!tribuf) { if (!tribuf) {
for (auto &c : cell->connections()) { for (auto &c : cell->connections()) {

4
passes/techmap/dff2dffe.cc
View File

@ -52,13 +52,13 @@ struct Dff2dffeWorker
} }
for (auto cell : module->cells()) { for (auto cell : module->cells()) {
if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$_MUX_") { if (cell->type.in("$mux", "$pmux", "$_MUX_")) {
RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y")); RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
for (int i = 0; i < GetSize(sig_y); i++) for (int i = 0; i < GetSize(sig_y); i++)
bit2mux[sig_y[i]] = cell_int_t(cell, i); bit2mux[sig_y[i]] = cell_int_t(cell, i);
} }
if (direct_dict.empty()) { if (direct_dict.empty()) {
if (cell->type == "$dff" || cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_") if (cell->type.in("$dff", "$_DFF_N_", "$_DFF_P_"))
dff_cells.push_back(cell); dff_cells.push_back(cell);
} else { } else {
if (direct_dict.count(cell->type)) if (direct_dict.count(cell->type))

2
passes/techmap/simplemap.cc
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@ -245,7 +245,7 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_b = cell->getPort("\\B"); RTLIL::SigSpec sig_b = cell->getPort("\\B");
RTLIL::SigSpec sig_y = cell->getPort("\\Y"); RTLIL::SigSpec sig_y = cell->getPort("\\Y");
bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool(); bool is_signed = cell->parameters.at("\\A_SIGNED").as_bool();
bool is_ne = cell->type == "$ne" || cell->type == "$nex"; bool is_ne = cell->type.in("$ne", "$nex");
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b))); RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed); RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);

22
techlibs/coolrunner2/coolrunner2_sop.cc
View File

@ -60,10 +60,8 @@ struct Coolrunner2SopPass : public Pass {
dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_inv; dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_inv;
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
{ {
if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" || if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\FTCP", "\\FTCP_N", "\\FTDCP",
cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" || "\\FDCPE", "\\FDCPE_N", "\\FDDCPE", "\\LDCP", "\\LDCP_N"))
cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE" ||
cell->type == "\\LDCP" || cell->type == "\\LDCP_N")
{ {
if (cell->hasPort("\\PRE")) if (cell->hasPort("\\PRE"))
special_pterms_no_inv[sigmap(cell->getPort("\\PRE")[0])].insert( special_pterms_no_inv[sigmap(cell->getPort("\\PRE")[0])].insert(
@ -257,10 +255,8 @@ struct Coolrunner2SopPass : public Pass {
pool<SigBit> sig_fed_by_ff; pool<SigBit> sig_fed_by_ff;
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
{ {
if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" || if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
cell->type == "\\LDCP" || cell->type == "\\LDCP_N" || "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE")
{ {
auto output = sigmap(cell->getPort("\\Q")[0]); auto output = sigmap(cell->getPort("\\Q")[0]);
sig_fed_by_ff.insert(output); sig_fed_by_ff.insert(output);
@ -270,13 +266,11 @@ struct Coolrunner2SopPass : public Pass {
// Look at all the FF inputs // Look at all the FF inputs
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
{ {
if (cell->type == "\\FDCP" || cell->type == "\\FDCP_N" || cell->type == "\\FDDCP" || if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
cell->type == "\\LDCP" || cell->type == "\\LDCP_N" || "\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP" ||
cell->type == "\\FDCPE" || cell->type == "\\FDCPE_N" || cell->type == "\\FDDCPE")
{ {
SigBit input; SigBit input;
if (cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP") if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
input = sigmap(cell->getPort("\\T")[0]); input = sigmap(cell->getPort("\\T")[0]);
else else
input = sigmap(cell->getPort("\\D")[0]); input = sigmap(cell->getPort("\\D")[0]);
@ -300,7 +294,7 @@ struct Coolrunner2SopPass : public Pass {
xor_cell->setPort("\\IN_PTC", and_to_xor_wire); xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
xor_cell->setPort("\\OUT", xor_to_ff_wire); xor_cell->setPort("\\OUT", xor_to_ff_wire);
if (cell->type == "\\FTCP" || cell->type == "\\FTCP_N" || cell->type == "\\FTDCP") if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
cell->setPort("\\T", xor_to_ff_wire); cell->setPort("\\T", xor_to_ff_wire);
else else
cell->setPort("\\D", xor_to_ff_wire); cell->setPort("\\D", xor_to_ff_wire);