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Merge pull request #1209 from YosysHQ/eddie/synth_xilinx 

[WIP] synth xilinx renaming, as per #1184
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Eddie Hung 2019-08-20 12:55:26 -07:00 committed by GitHub
parent 14c03861b6 d9fe4cccbf
commit 33960dd3d8
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 23 additions and 16 deletions
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4
CHANGELOG
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@ -14,6 +14,10 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added "synth -abc9" (experimental) - Added "synth -abc9" (experimental)
- Added "script -scriptwire - Added "script -scriptwire
- "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable) - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
- Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
- Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
- Renamed labels in synth_intel (e.g. bram -> map_bram)
- Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
- Added automatic gzip decompression for frontends - Added automatic gzip decompression for frontends
- Added $_NMUX_ cell type - Added $_NMUX_ cell type
- Added automatic gzip compression (based on filename extension) for backends - Added automatic gzip compression (based on filename extension) for backends

4
techlibs/xilinx/Makefile.inc
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@ -32,8 +32,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))

0
techlibs/xilinx/drams.txt → techlibs/xilinx/lutrams.txt
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0
techlibs/xilinx/drams_map.v → techlibs/xilinx/lutrams_map.v
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31
techlibs/xilinx/synth_xilinx.cc
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@ -64,13 +64,13 @@ struct SynthXilinxPass : public ScriptPass
log(" (this feature is experimental and incomplete)\n"); log(" (this feature is experimental and incomplete)\n");
log("\n"); log("\n");
log(" -nobram\n"); log(" -nobram\n");
log(" disable inference of block rams\n"); log(" do not use block RAM cells in output netlist\n");
log("\n"); log("\n");
log(" -nodram\n"); log(" -nolutram\n");
log(" disable inference of distributed rams\n"); log(" do not use distributed RAM cells in output netlist\n");
log("\n"); log("\n");
log(" -nosrl\n"); log(" -nosrl\n");
log(" disable inference of shift registers\n"); log(" do not use distributed SRL cells in output netlist\n");
log("\n"); log("\n");
log(" -nocarry\n"); log(" -nocarry\n");
log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n"); log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n");
@ -104,7 +104,7 @@ struct SynthXilinxPass : public ScriptPass
} }
std::string top_opt, edif_file, blif_file, family; std::string top_opt, edif_file, blif_file, family;
bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9; bool flatten, retime, vpr, nobram, nolutram, nosrl, nocarry, nowidelut, abc9;
int widemux; int widemux;
void clear_flags() YS_OVERRIDE void clear_flags() YS_OVERRIDE
@ -118,7 +118,7 @@ struct SynthXilinxPass : public ScriptPass
vpr = false; vpr = false;
nocarry = false; nocarry = false;
nobram = false; nobram = false;
nodram = false; nolutram = false;
nosrl = false; nosrl = false;
nocarry = false; nocarry = false;
nowidelut = false; nowidelut = false;
@ -186,8 +186,8 @@ struct SynthXilinxPass : public ScriptPass
nobram = true; nobram = true;
continue; continue;
} }
if (args[argidx] == "-nodram") { if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") {
nodram = true; nolutram = true;
continue; continue;
} }
if (args[argidx] == "-nosrl") { if (args[argidx] == "-nosrl") {
@ -284,7 +284,7 @@ struct SynthXilinxPass : public ScriptPass
run("opt_clean"); run("opt_clean");
} }
if (check_label("bram", "(skip if '-nobram')")) { if (check_label("map_bram", "(skip if '-nobram')")) {
if (help_mode) { if (help_mode) {
run("memory_bram -rules +/xilinx/{family}_brams.txt"); run("memory_bram -rules +/xilinx/{family}_brams.txt");
run("techmap -map +/xilinx/{family}_brams_map.v"); run("techmap -map +/xilinx/{family}_brams_map.v");
@ -301,20 +301,23 @@ struct SynthXilinxPass : public ScriptPass
} }
} }
if (check_label("dram", "(skip if '-nodram')")) { if (check_label("map_lutram", "(skip if '-nolutram')")) {
if (!nodram || help_mode) { if (!nolutram || help_mode) {
run("memory_bram -rules +/xilinx/drams.txt"); run("memory_bram -rules +/xilinx/lutrams.txt");
run("techmap -map +/xilinx/drams_map.v"); run("techmap -map +/xilinx/lutrams_map.v");
} }
} }
if (check_label("fine")) { if (check_label("map_ffram")) {
if (widemux > 0) if (widemux > 0)
run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover
// performs less efficiently // performs less efficiently
else else
run("opt -fast -full"); run("opt -fast -full");
run("memory_map"); run("memory_map");
}
if (check_label("fine")) {
run("dffsr2dff"); run("dffsr2dff");
run("dff2dffe"); run("dff2dffe");
if (help_mode) { if (help_mode) {