From b97fe6e86651b3a4736c46a49d76878beb088a8c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 14:20:43 -0700 Subject: [PATCH 1/5] Work in progress for renaming labels/options in synth_xilinx --- techlibs/xilinx/{drams.txt => lutrams.txt} | 0 .../xilinx/{drams_map.v => lutrams_map.v} | 0 techlibs/xilinx/synth_xilinx.cc | 31 ++++++++++--------- 3 files changed, 17 insertions(+), 14 deletions(-) rename techlibs/xilinx/{drams.txt => lutrams.txt} (100%) rename techlibs/xilinx/{drams_map.v => lutrams_map.v} (100%) diff --git a/techlibs/xilinx/drams.txt b/techlibs/xilinx/lutrams.txt similarity index 100% rename from techlibs/xilinx/drams.txt rename to techlibs/xilinx/lutrams.txt diff --git a/techlibs/xilinx/drams_map.v b/techlibs/xilinx/lutrams_map.v similarity index 100% rename from techlibs/xilinx/drams_map.v rename to techlibs/xilinx/lutrams_map.v diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index b672a0d4f..a6c1fa873 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -64,13 +64,13 @@ struct SynthXilinxPass : public ScriptPass log(" (this feature is experimental and incomplete)\n"); log("\n"); log(" -nobram\n"); - log(" disable inference of block rams\n"); + log(" do not use block RAM cells in output netlist\n"); log("\n"); - log(" -nodram\n"); - log(" disable inference of distributed rams\n"); + log(" -nolutram\n"); + log(" do not use distributed RAM cells in output netlist\n"); log("\n"); log(" -nosrl\n"); - log(" disable inference of shift registers\n"); + log(" do not use distributed SRL cells in output netlist\n"); log("\n"); log(" -nocarry\n"); log(" do not use XORCY/MUXCY/CARRY4 cells in output netlist\n"); @@ -104,7 +104,7 @@ struct SynthXilinxPass : public ScriptPass } std::string top_opt, edif_file, blif_file, family; - bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9; + bool flatten, retime, vpr, nobram, nolutram, nosrl, nocarry, nowidelut, abc9; int widemux; void clear_flags() YS_OVERRIDE @@ -118,7 +118,7 @@ struct SynthXilinxPass : public ScriptPass vpr = false; nocarry = false; nobram = false; - nodram = false; + nolutram = false; nosrl = false; nocarry = false; nowidelut = false; @@ -186,8 +186,8 @@ struct SynthXilinxPass : public ScriptPass nobram = true; continue; } - if (args[argidx] == "-nodram") { - nodram = true; + if (args[argidx] == "-nolutram" || /*deprecated alias*/ args[argidx] == "-nodram") { + nolutram = true; continue; } if (args[argidx] == "-nosrl") { @@ -284,7 +284,7 @@ struct SynthXilinxPass : public ScriptPass run("opt_clean"); } - if (check_label("bram", "(skip if '-nobram')")) { + if (check_label("map_bram", "(skip if '-nobram')")) { if (help_mode) { run("memory_bram -rules +/xilinx/{family}_brams.txt"); run("techmap -map +/xilinx/{family}_brams_map.v"); @@ -301,20 +301,23 @@ struct SynthXilinxPass : public ScriptPass } } - if (check_label("dram", "(skip if '-nodram')")) { - if (!nodram || help_mode) { - run("memory_bram -rules +/xilinx/drams.txt"); - run("techmap -map +/xilinx/drams_map.v"); + if (check_label("map_lutram", "(skip if '-nolutram')")) { + if (!nolutram || help_mode) { + run("memory_bram -rules +/xilinx/lutrams.txt"); + run("techmap -map +/xilinx/lutrams_map.v"); } } - if (check_label("fine")) { + if (check_label("map_ffram")) { if (widemux > 0) run("opt -fast -mux_bool -undriven -fine"); // Necessary to omit -mux_undef otherwise muxcover // performs less efficiently else run("opt -fast -full"); run("memory_map"); + } + + if (check_label("fine")) { run("dffsr2dff"); run("dff2dffe"); if (help_mode) { From 4b71e6c42155d3359e0cca8529c12799209cf808 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 14:21:04 -0700 Subject: [PATCH 2/5] Add CHANGELOG entry --- CHANGELOG | 3 +++ 1 file changed, 3 insertions(+) diff --git a/CHANGELOG b/CHANGELOG index 44d83c1bf..b475ae423 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -14,6 +14,9 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "synth -abc9" (experimental) - Added "script -scriptwire - "synth_xilinx" to now infer wide multiplexers (-widemux to enable) + - Renamed labels/options in synth_ice40 (e.g. map_dram -> map_lutram; -nodram -> -nolutram) + - Renamed labels/options in synth_ecp5 (e.g. map_dram -> map_lutram; -nodram -> -nolutram) + - Renamed labels/options in synth_xilinx (e.g. map_dram -> map_lutram; -nodram -> -nolutram) Yosys 0.8 .. Yosys 0.8-dev From 43616e1414ed3d98b44c4a55f4d08e2d10664aa1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 18 Jul 2019 14:51:55 -0700 Subject: [PATCH 3/5] Update Makefile too --- techlibs/xilinx/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 2c6e7432e..2b1af289c 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -32,8 +32,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) From 280288a62abb97b4ffe8e3bc56896811f291bab5 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 22 Jul 2019 07:46:06 -0700 Subject: [PATCH 4/5] Update changelog --- CHANGELOG | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index b475ae423..b82a62495 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -14,9 +14,10 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "synth -abc9" (experimental) - Added "script -scriptwire - "synth_xilinx" to now infer wide multiplexers (-widemux to enable) - - Renamed labels/options in synth_ice40 (e.g. map_dram -> map_lutram; -nodram -> -nolutram) - - Renamed labels/options in synth_ecp5 (e.g. map_dram -> map_lutram; -nodram -> -nolutram) - - Renamed labels/options in synth_xilinx (e.g. map_dram -> map_lutram; -nodram -> -nolutram) + - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram) + - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram) + - Renamed labels in synth_intel (e.g. bram -> map_bram) + - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram) Yosys 0.8 .. Yosys 0.8-dev From 297a9802122817e143b1e4b87fd0d4e357606a72 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 25 Jul 2019 10:44:20 -0700 Subject: [PATCH 5/5] Bump abc to fix &mfs bug --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index d33f27b63..3bc119800 100644 --- a/Makefile +++ b/Makefile @@ -122,7 +122,7 @@ OBJS = kernel/version_$(GIT_REV).o # is just a symlink to your actual ABC working directory, as 'make mrproper' # will remove the 'abc' directory and you do not want to accidentally # delete your work on ABC.. -ABCREV = 62487de +ABCREV = 5776ad0 ABCPULL = 1 ABCURL ?= https://github.com/berkeley-abc/abc ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1