mirror of https://github.com/YosysHQ/yosys.git
- frontends/vhdl2verilog/vhdl2verilog.cc, passes/abc/abc.cc: #include <climits> for PATH_MAX.
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@ -27,6 +27,7 @@
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#include <string.h>
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#include <dirent.h>
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#include <errno.h>
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#include <limits.h>
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struct Vhdl2verilogPass : public Pass {
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Vhdl2verilogPass() : Pass("vhdl2verilog", "importing VHDL designs using vhdl2verilog") { }
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@ -45,6 +45,7 @@
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#include <dirent.h>
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#include <cerrno>
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#include <sstream>
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#include <climits>
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#include "blifparse.h"
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