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Get rid of compiler warnings

This commit is contained in:
Eddie Hung 2019-06-14 13:07:56 -07:00
parent 8fa74287a7
commit 2d85725604
2 changed files with 7 additions and 7 deletions
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4
backends/aiger/xaiger.cc
View File

@ -190,7 +190,7 @@ struct XAigerWriter
bool abc_box_seen = false; bool abc_box_seen = false;
for (auto cell : module->cells()) { for (auto cell : module->selected_cells()) {
if (cell->type == "$_NOT_") if (cell->type == "$_NOT_")
{ {
SigBit A = sigmap(cell->getPort("\\A").as_bit()); SigBit A = sigmap(cell->getPort("\\A").as_bit());
@ -312,7 +312,7 @@ struct XAigerWriter
TopoSort<IdString, RTLIL::sort_by_id_str> toposort; TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
dict<SigBit, pool<IdString>> bit_drivers, bit_users; dict<SigBit, pool<IdString>> bit_drivers, bit_users;
for (auto cell : module->cells()) { for (auto cell : module->selected_cells()) {
RTLIL::Module* inst_module = module->design->module(cell->type); RTLIL::Module* inst_module = module->design->module(cell->type);
if (!inst_module || !inst_module->attributes.count("\\abc_box_id")) if (!inst_module || !inst_module->attributes.count("\\abc_box_id"))
continue; continue;

10
passes/techmap/abc9.cc
View File

@ -243,8 +243,8 @@ struct abc_output_filter
void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file, void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str, bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
bool keepff, std::string delay_target, std::string lutin_shared, bool fast_mode, bool /*keepff*/, std::string delay_target, std::string /*lutin_shared*/, bool fast_mode,
const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, std::string box_file, std::string lut_file, bool show_tempdir, std::string box_file, std::string lut_file,
std::string wire_delay) std::string wire_delay)
{ {
module = current_module; module = current_module;
@ -835,7 +835,7 @@ struct Abc9Pass : public Pass {
std::string script_file, clk_str, box_file, lut_file; std::string script_file, clk_str, box_file, lut_file;
std::string delay_target, lutin_shared = "-S 1", wire_delay; std::string delay_target, lutin_shared = "-S 1", wire_delay;
bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true; bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
bool show_tempdir = false, sop_mode = false; bool show_tempdir = false;
vector<int> lut_costs; vector<int> lut_costs;
markgroups = false; markgroups = false;
@ -997,7 +997,7 @@ struct Abc9Pass : public Pass {
if (!dff_mode || !clk_str.empty()) { if (!dff_mode || !clk_str.empty()) {
abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, dff_mode, clk_str, keepff, abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
delay_target, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, delay_target, lutin_shared, fast_mode, show_tempdir,
box_file, lut_file, wire_delay); box_file, lut_file, wire_delay);
continue; continue;
} }
@ -1143,7 +1143,7 @@ struct Abc9Pass : public Pass {
en_polarity = std::get<2>(it.first); en_polarity = std::get<2>(it.first);
en_sig = assign_map(std::get<3>(it.first)); en_sig = assign_map(std::get<3>(it.first));
abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, !clk_sig.empty(), "$", abc9_module(design, mod, script_file, exe_file, cleanup, lut_costs, !clk_sig.empty(), "$",
keepff, delay_target, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, keepff, delay_target, lutin_shared, fast_mode, show_tempdir,
box_file, lut_file, wire_delay); box_file, lut_file, wire_delay);
assign_map.set(mod); assign_map.set(mod);
} }